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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- June, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS241N: Octal buffer/line driver (3-state ops) --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_241 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '1';
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Period : time := 50 ns;
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Finish : time := 20 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_241 is
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signal RS : std_logic;
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signal CLK : std_logic;
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signal JC, BC : unsigned(9 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
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signal OEA, OEB : std_logic;
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signal IA, IB : std_logic_vector(3 downto 0);
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begin
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OEA <= JC(9);
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OEB <= JC(8);
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IA <= std_logic_vector(BC(4 downto 1));
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IB <= std_logic_vector(BC(3 downto 0));
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => JC,
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B => BC,
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CLK => CLK,
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RS => RS,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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GG: for j in IA'range generate
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begin
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D(j) <= IA(j) when OEA = '0' else 'Z';
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D(j+4) <= IB(j) when OEB = '1' else 'Z';
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end generate;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS241N
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port map(
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X_1 => OEA, -- OEA\
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X_2 => IA(0), -- IA0
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X_3 => E(4), -- YB0
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X_4 => IA(1), -- IA1
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X_5 => E(5), -- YB1
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X_6 => IA(2), -- IA2
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X_7 => E(6), -- YB2
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X_8 => IA(3), -- IA3
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X_9 => E(7), -- YB3
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X_10 => open, -- GND
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X_11 => IB(3), -- IB3
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X_12 => E(3), -- YA3
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X_13 => IB(2), -- IB2
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X_14 => E(2), -- YA2
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X_15 => IB(1), -- IB1
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X_16 => E(1), -- YA1
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X_17 => IB(0), -- IB0
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X_18 => E(0), -- YA0
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X_19 => OEB, -- OEB
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X_20 => open -- Vcc
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);
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end architecture Test;
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