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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_258.vhd] - Blame information for rev 3

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- December, 2016.  Perth, Australia                                 --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS258N: Quad 2-input mux (3-state inverting)    --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_258 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           :=  50 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_258 is
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    signal J, B : unsigned(9 downto 0);         -- Test stimuli
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    signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J   => J,
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        B   => B,
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        CLK => open,
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        RS  => open,
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        D   => D,
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        E   => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(B) is
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        variable Z : std_logic_vector(3 downto 0);
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    begin
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        if B(0) = '1' then
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            Z := (others => 'Z');
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        elsif B(1) = '0' then
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            Z := (B(8), B(6), B(4), B(2));
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        else
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            Z := (B(9), B(7), B(5), B(3));
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        end if;
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        for i in Z'range loop
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            if Z(i) = 'Z' then
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                D(i) <= 'Z';
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            else
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                D(i) <= not Z(i);
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            end if;
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        end loop;
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74LS258N
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    port map(
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    X_1  => B(1),  -- S
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    X_2  => B(2),  -- I0A
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    X_3  => B(3),  -- I1A
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    X_4  => E(0),  -- ZA
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    X_5  => B(4),  -- I0B
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    X_6  => B(5),  -- I1B
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    X_7  => E(1),  -- ZB
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    X_8  => open,  -- GND
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    X_9  => E(3),  -- ZD
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    X_10 => B(9),  -- I1D
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    X_11 => B(8),  -- I0D
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    X_12 => E(2),  -- ZC
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    X_13 => B(7),  -- I1C
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    X_14 => B(6),  -- I0C
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    X_15 => B(0),  -- E\
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    X_16 => open   -- Vcc
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);
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end architecture Test;

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