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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_273.vhd] - Blame information for rev 3
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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- December, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS273N: 8-bit D-type register with clear --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_273 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '1';
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Period : time := 100 ns;
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Finish : time := 20 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_273 is
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signal RS : std_logic;
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signal CLK : std_logic;
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signal JC, BC : unsigned(7 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
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begin
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => JC,
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B => BC,
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CLK => CLK,
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RS => RS,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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process(CLK, RS) is
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begin
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if RS = '0' then
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D <= (others => '0');
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elsif rising_edge(CLK) then
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D <= std_logic_vector(BC);
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end if;
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end process;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS273N
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port map(
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X_1 => RS, -- MR\
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X_2 => E(0), -- Q0
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X_3 => BC(0), -- D0
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X_4 => BC(1), -- D1
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X_5 => E(1), -- Q1
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X_6 => E(2), -- Q2
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X_7 => BC(2), -- D2
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X_8 => BC(3), -- D3
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X_9 => E(3), -- Q3
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X_10 => open, -- GND
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X_11 => CLK, -- CP
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X_12 => E(4), -- Q4
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X_13 => BC(4), -- D4
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X_14 => BC(5), -- D5
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X_15 => E(5), -- Q5
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X_16 => E(6), -- Q6
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X_17 => BC(6), -- D6
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X_18 => BC(7), -- D7
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X_19 => E(7), -- Q7
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X_20 => open -- Vcc
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);
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end architecture Test;
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