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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- December, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS279N: 4-bit S-R latch --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_279 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '0';
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Period : time := 100 ns;
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Finish : time := 20 us;
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SevLevel : severity_level := warning
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);
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end entity;
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architecture Test of Testbench_279 is
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signal J, B : unsigned(11 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
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signal X : std_logic_vector(11 downto 0); -- Shortened R-X-S pulses
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signal CLK, RS : std_logic;
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begin
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => J,
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B => B,
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CLK => CLK,
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RS => RS,
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D => D,
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E => E
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);
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process(CLK, RS) is -- Generate short R-S pulses
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variable Y : std_logic_vector(11 downto 0);
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begin
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if RS = '0' then
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X <= "011011011011"; -- General reset
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elsif rising_edge(CLK) then
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Y := std_logic_vector(J);
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Y(9) := Y(9) or not Y(11); -- Reset dominates, all cases
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Y(6) := Y(6) or not (Y(7) and Y(8));
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Y(3) := Y(3) or not Y(5);
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Y(1) := Y(1) or not Y(2);
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Y(0) := Y(0) or not Y(2);
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X <= Y, (others => '1') after Period / 2;
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end if;
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end process;
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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process(all) is
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variable R, S : std_logic_vector(3 downto 0);
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variable Z : std_logic_vector(1 downto 0);
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begin
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R := (X(11), X(8) and X(7), X(5), X(2));
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S := (X(9), X(6), X(3), X(1) and X(0));
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for i in R'range loop
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Z := S(i) & R(i);
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case Z is
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when "11" => null;
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when "01" => D(i) <= '1';
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when "10" => D(i) <= '0';
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when others => D(i) <= 'X';
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end case;
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end loop;
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end process;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS279N
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port map(
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X_1 => X(2), -- 1R\
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X_2 => X(1), -- 1S1\
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X_3 => X(0), -- 1S2\
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X_4 => E(0), -- 1Q
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X_5 => X(5), -- 2R\
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X_6 => X(3), -- 2S\
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X_7 => E(1), -- 2Q
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X_8 => open, -- GND
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X_9 => E(2), -- 3Q
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X_10 => X(6), -- 3S\
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X_11 => X(7), -- 3R1\
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X_12 => X(8), -- 3R2\
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X_13 => E(3), -- 4Q
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X_14 => X(9), -- 4S\
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X_15 => X(11), -- 4R\
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X_16 => open -- Vcc
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);
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end architecture Test;
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