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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- December, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS322N: 8 bit ser/par register + sign extend --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_322 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '1';
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Period : time := 40 ns;
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Finish : time := 50 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_322 is
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signal J, B : unsigned(14 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(8 downto 0); -- Expected & actual results
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signal RS, CLK : std_logic;
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signal OEI, DIN : std_logic;
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signal DI, R, DT : std_logic_vector(7 downto 0);
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alias RE is J(8);
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alias SP is J(9);
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alias D0 is J(10);
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alias D1 is J(11);
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alias OE is J(12);
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alias SE is J(13);
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alias S is J(14);
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begin
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OEI <= (SP or RE) and not(OE);
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DIN <= D0 when S = '0' else D1;
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DI <= std_logic_vector(J(7 downto 0)) when OE = '1' else (others => 'Z');
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E <= "Z" & DI;
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DT <= std_logic_vector(J(7 downto 0)) when OE = '1' else
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R when OEI = '1' else
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(others => 'Z');
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D <= R(0) & DT;
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => J,
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B => B,
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CLK => CLK,
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RS => RS,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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process(RS, CLK) is
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variable SEL : unsigned(2 downto 0);
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begin
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if RS = '0' then
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R <= (others => '0');
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elsif rising_edge(CLK) then
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SEL := RE & SP & SE;
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case SEL is
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when "011" => R <= DIN & R(7 downto 1); -- Shift right
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when "010" => R <= R(7) & R(7 downto 1); -- Shift left
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when "00-" => R <= DT; -- Parallel load
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when others => null; -- Hold
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end case;
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end if;
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end process;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS322N
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port map(
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X_1 => RE, -- RE\
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X_2 => SP, -- S/P\
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X_3 => D0, -- D0
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X_4 => DI(7), -- IO7
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X_5 => DI(5), -- IO5
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X_6 => DI(3), -- IO3
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X_7 => DI(1), -- IO1
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X_8 => OE, -- OE\
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X_9 => RS, -- MR\
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X_10 => open, -- GND
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X_11 => CLK, -- CP
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X_12 => E(8), -- Q0
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X_13 => DI(0), -- IO0
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X_14 => DI(2), -- IO2
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X_15 => DI(4), -- IO4
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X_16 => DI(6), -- IO6
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X_17 => D1, -- D1
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X_18 => SE, -- SE\
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X_19 => S, -- S
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X_20 => open -- Vcc
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);
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end architecture Test;
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