OpenCores
URL https://opencores.org/ocsvn/ttl_library/ttl_library/trunk

Subversion Repositories ttl_library

[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_368.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 david237
-----------------------------------------------------------------------
2
-- Bipolar TTL models (VHDL)                                         --
3
-- David R Brooks                                                    --
4
-- December, 2016.  Perth, Australia                                 --
5
-- Compliance: VHDL 2008                                             --
6
-- Testbench for SN74LS367N: 2- & 4-bit 3-state buffer (inverting)   --
7
-----------------------------------------------------------------------
8
 
9
library ieee;
10
    use ieee.std_logic_1164.all;
11
    use ieee.std_logic_misc.all;
12
    use ieee.numeric_std.all;
13
    use work.LSTTL.all;
14
    use work.TTLPrivate.all;
15
 
16
entity Testbench_368 is     -- Top-level bench
17
generic(
18
    StimClk  : std_logic      := '1';
19
    CheckClk : std_logic      := '1';
20
    Period   : time           :=  50 ns;
21
    Finish   : time           := 200 us;
22
    SevLevel : severity_level := failure
23
);
24
end entity;
25
 
26
architecture Test of Testbench_368 is
27
    signal J, B : unsigned(5 downto 0);         -- Test stimuli
28
    signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
29
 
30
    begin
31
 
32
    -----------------------------------------------------------------------
33
    -- Standard testbench components
34
    -----------------------------------------------------------------------
35
    TB: TTLBench
36
    generic map(
37
        StimClk  => StimClk,
38
        CheckClk => CheckClk,
39
        Period   => Period,
40
        Finish   => Finish,
41
        SevLevel => SevLevel
42
    )
43
    port map(
44
        J   => J,
45
        B   => B,
46
        CLK => open,
47
        RS  => open,
48
        D   => D,
49
        E   => E
50
    );
51
 
52
    -----------------------------------------------------------------------
53
    -- Generate expected results (with zero delays)
54
    -----------------------------------------------------------------------
55
    G: for i in B'range generate
56
        signal EN : std_logic;
57
    begin
58
        EN <= J(1) when i > 3 else J(0);
59
        D(i) <= not B(i) when EN = '0' else 'Z';
60
    end generate;
61
 
62
    -----------------------------------------------------------------------
63
    -- Device Under Test...                        
64
    -----------------------------------------------------------------------
65
    DUT: SN74LS368AN
66
    port map(
67
        X_1  => J(0),  -- E1\
68
        X_2  => B(0),  -- A1
69
        X_3  => E(0),  -- Y1\
70
        X_4  => B(1),  -- A2
71
        X_5  => E(1),  -- Y2\
72
        X_6  => B(2),  -- A3
73
        X_7  => E(2),  -- Y3\
74
        X_8  => open,  -- GND
75
        X_9  => E(3),  -- Y4\
76
        X_10 => B(3),  -- A4
77
        X_11 => E(4),  -- Y5\
78
        X_12 => B(4),  -- A5
79
        X_13 => E(5),  -- Y6\
80
        X_14 => B(5),  -- A6
81
        X_15 => J(1),  -- E2\
82
        X_16 => open   -- Vcc
83
);
84
end architecture Test;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.