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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_368.vhd] - Blame information for rev 5
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david237 |
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL) --
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-- David R Brooks --
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-- December, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for SN74LS367N: 2- & 4-bit 3-state buffer (inverting) --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.LSTTL.all;
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use work.TTLPrivate.all;
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entity Testbench_368 is -- Top-level bench
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generic(
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StimClk : std_logic := '1';
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CheckClk : std_logic := '1';
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Period : time := 50 ns;
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Finish : time := 200 us;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_368 is
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signal J, B : unsigned(5 downto 0); -- Test stimuli
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signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
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begin
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => J,
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B => B,
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CLK => open,
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RS => open,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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G: for i in B'range generate
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signal EN : std_logic;
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begin
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EN <= J(1) when i > 3 else J(0);
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D(i) <= not B(i) when EN = '0' else 'Z';
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end generate;
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: SN74LS368AN
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port map(
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X_1 => J(0), -- E1\
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X_2 => B(0), -- A1
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X_3 => E(0), -- Y1\
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X_4 => B(1), -- A2
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X_5 => E(1), -- Y2\
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X_6 => B(2), -- A3
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X_7 => E(2), -- Y3\
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X_8 => open, -- GND
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X_9 => E(3), -- Y4\
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X_10 => B(3), -- A4
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X_11 => E(4), -- Y5\
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X_12 => B(4), -- A5
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X_13 => E(5), -- Y6\
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X_14 => B(5), -- A6
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X_15 => J(1), -- E2\
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X_16 => open -- Vcc
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);
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end architecture Test;
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