URL
https://opencores.org/ocsvn/ttl_library/ttl_library/trunk
[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_374.vhd] - Blame information for rev 3
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
3 |
david237 |
-----------------------------------------------------------------------
|
| 2 |
|
|
-- Bipolar TTL models (VHDL) --
|
| 3 |
|
|
-- David R Brooks --
|
| 4 |
|
|
-- December, 2016. Perth, Australia --
|
| 5 |
|
|
-- Compliance: VHDL 2008 --
|
| 6 |
|
|
-- Testbench for SN74LS374N: 8-bit D flipflop --
|
| 7 |
|
|
-----------------------------------------------------------------------
|
| 8 |
|
|
|
| 9 |
|
|
library ieee;
|
| 10 |
|
|
use ieee.std_logic_1164.all;
|
| 11 |
|
|
use ieee.std_logic_misc.all;
|
| 12 |
|
|
use ieee.numeric_std.all;
|
| 13 |
|
|
use work.LSTTL.all;
|
| 14 |
|
|
use work.TTLPrivate.all;
|
| 15 |
|
|
|
| 16 |
|
|
entity Testbench_374 is -- Top-level bench
|
| 17 |
|
|
generic(
|
| 18 |
|
|
StimClk : std_logic := '1';
|
| 19 |
|
|
CheckClk : std_logic := '0';
|
| 20 |
|
|
Period : time := 100 ns;
|
| 21 |
|
|
Finish : time := 20 us;
|
| 22 |
|
|
SevLevel : severity_level := failure
|
| 23 |
|
|
);
|
| 24 |
|
|
end entity;
|
| 25 |
|
|
|
| 26 |
|
|
architecture Test of Testbench_374 is
|
| 27 |
|
|
signal J, B : unsigned(7 downto 0); -- Test stimuli
|
| 28 |
|
|
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
|
| 29 |
|
|
signal R : std_logic_vector(7 downto 0); -- Latch
|
| 30 |
|
|
signal CLK : std_logic;
|
| 31 |
|
|
|
| 32 |
|
|
alias OE is J(0);
|
| 33 |
|
|
|
| 34 |
|
|
begin
|
| 35 |
|
|
-----------------------------------------------------------------------
|
| 36 |
|
|
-- Standard testbench components
|
| 37 |
|
|
-----------------------------------------------------------------------
|
| 38 |
|
|
TB: TTLBench
|
| 39 |
|
|
generic map(
|
| 40 |
|
|
StimClk => StimClk,
|
| 41 |
|
|
CheckClk => CheckClk,
|
| 42 |
|
|
Period => Period,
|
| 43 |
|
|
Finish => Finish,
|
| 44 |
|
|
SevLevel => SevLevel
|
| 45 |
|
|
)
|
| 46 |
|
|
port map(
|
| 47 |
|
|
J => J,
|
| 48 |
|
|
B => B,
|
| 49 |
|
|
CLK => CLK,
|
| 50 |
|
|
RS => open,
|
| 51 |
|
|
D => D,
|
| 52 |
|
|
E => E
|
| 53 |
|
|
);
|
| 54 |
|
|
|
| 55 |
|
|
-----------------------------------------------------------------------
|
| 56 |
|
|
-- Generate expected results (with zero delays)
|
| 57 |
|
|
-----------------------------------------------------------------------
|
| 58 |
|
|
process(CLK) is
|
| 59 |
|
|
begin
|
| 60 |
|
|
if rising_edge(CLK) then
|
| 61 |
|
|
R <= std_logic_vector(B);
|
| 62 |
|
|
end if;
|
| 63 |
|
|
end process;
|
| 64 |
|
|
|
| 65 |
|
|
D <= R when OE = '0' else (others => 'Z');
|
| 66 |
|
|
|
| 67 |
|
|
-----------------------------------------------------------------------
|
| 68 |
|
|
-- Device Under Test...
|
| 69 |
|
|
-----------------------------------------------------------------------
|
| 70 |
|
|
DUT: SN74LS374N
|
| 71 |
|
|
port map(
|
| 72 |
|
|
X_1 => OE, -- OE\
|
| 73 |
|
|
X_2 => E(0), -- Q0
|
| 74 |
|
|
X_3 => B(0), -- D0
|
| 75 |
|
|
X_4 => B(1), -- D1
|
| 76 |
|
|
X_5 => E(1), -- Q1
|
| 77 |
|
|
X_6 => E(2), -- Q2
|
| 78 |
|
|
X_7 => B(2), -- D2
|
| 79 |
|
|
X_8 => B(3), -- D3
|
| 80 |
|
|
X_9 => E(3), -- Q3
|
| 81 |
|
|
X_10 => open, -- GND
|
| 82 |
|
|
X_11 => CLK, -- CP
|
| 83 |
|
|
X_12 => E(4), -- Q4
|
| 84 |
|
|
X_13 => B(4), -- D4
|
| 85 |
|
|
X_14 => B(5), -- D5
|
| 86 |
|
|
X_15 => E(5), -- Q5
|
| 87 |
|
|
X_16 => E(6), -- Q6
|
| 88 |
|
|
X_17 => B(6), -- D6
|
| 89 |
|
|
X_18 => B(7), -- D7
|
| 90 |
|
|
X_19 => E(7), -- Q7
|
| 91 |
|
|
X_20 => open -- Vcc
|
| 92 |
|
|
);
|
| 93 |
|
|
end architecture Test;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.