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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_540.vhd] - Blame information for rev 3

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- December, 2016.  Perth, Australia                                 --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS540N: Octal buffer/line driver (3-state ops)  --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_540 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 50 ns;
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    Finish   : time           := 20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_540 is
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    signal RS, OE   : std_logic;
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    signal CLK      : std_logic;
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    signal JC, BC   : unsigned(9 downto 0);       -- Test stimuli
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    signal D,  E    : std_logic_vector(7 downto 0);   -- Expected & actual results
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    signal I        : std_logic_vector(7 downto 0);
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    alias OEA is JC(9);
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    alias OEB is JC(8);
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begin
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    I  <= std_logic_vector(BC(7 downto 0));
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    OE <= not(OEA or OEB);
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    D <= not I when OE = '1' else (others => 'Z');
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74LS540N
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    port map(
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        X_1  => OEA,   -- E1\
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        X_2  => I(0),  -- A0
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        X_3  => I(1),  -- A1
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        X_4  => I(2),  -- A2
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        X_5  => I(3),  -- A3
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        X_6  => I(4),  -- A4
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        X_7  => I(5),  -- A5
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        X_8  => I(6),  -- A6
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        X_9  => I(7),  -- A7
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        X_10 => open,  -- GND
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        X_11 => E(7),  -- Y7\
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        X_12 => E(6),  -- Y6\
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        X_13 => E(5),  -- Y5\
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        X_14 => E(4),  -- Y4\
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        X_15 => E(3),  -- Y3\
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        X_16 => E(2),  -- Y2\
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        X_17 => E(1),  -- Y1\
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        X_18 => E(0),  -- Y0\
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        X_19 => OEB,   -- E2\
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        X_20 => open   -- Vcc            
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    );
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end architecture Test;

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