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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_68.vhd] - Blame information for rev 11

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS68N: Dual 4-bit decade counter                --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_68 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      :=  '0';
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    CheckClk : std_logic      :=  '0';
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    Period   : time           := 120 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_68 is
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    signal RS, C0 : std_logic;
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    signal CLK    : std_logic;
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    signal J,  B  : unsigned(1 downto 0);           -- Test stimuli
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    signal D,  E  : std_logic_vector(7 downto 0);   -- Expected & actual results
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J   => J,
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        B   => B,
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        CLK => CLK,
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        RS  => RS,
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        D   => D,
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        E   => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    -- Low bits: the 2+5 counter
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    process(B, RS) is
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        variable Q0 : std_logic;
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    begin
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        if    RS = '0' then
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            Q0 := '0';
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        elsif falling_edge(B(0)) then
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            Q0 := not Q0;
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        end if;
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        D(0) <= Q0;
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    end process;
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    process(D, RS) is
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        variable Q31 : unsigned(2 downto 0);
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    begin
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        if    RS = '0' then
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            Q31 := (others => '0');
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        elsif falling_edge(D(0)) then
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            case TTL_to_integer(Q31) is
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                when 4 to 7 => Q31 := Q31 - 4;
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                when others => Q31 := Q31 + 1;
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            end case;
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        end if;
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        D(3 downto 1) <= std_logic_vector(Q31);
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    end process;
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    -- High bits: straight BCD counter
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    process(B, RS) is
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        variable Q30 : unsigned(3 downto 0);
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    begin
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        if    RS = '0' then
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            Q30 := (others => '0');
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        elsif falling_edge(B(1)) then
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            case TTL_to_integer(Q30) is
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                when      9 => Q30 := "0000";
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                when     11 => Q30 := "0010";
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                when     13 => Q30 := "0100";
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                when     15 => Q30 := "0110";
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                when others => Q30 := Q30 + 1;
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            end case;
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        end if;
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        D(7 downto 4) <= std_logic_vector(Q30);
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74LS68N
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    port map(
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    X_1  => B(0),  -- 1CLKA
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    X_2  => E(1),  -- 1QB
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    X_3  => E(3),  -- 1QD
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    X_4  => RS,    -- \1CLR
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    X_5  => E(6),  -- 2QC
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                   -- 
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    X_7  => E(4),  -- 2QA
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    X_8  => open,  -- GND
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    X_9  => B(1),  -- 2CLK
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    X_10 => E(5),  -- 2QB
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    X_11 => RS,    -- \2CLR
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    X_12 => E(7),  -- 2QD
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    X_13 => E(2),  -- 1QC
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    X_14 => C0,    -- 1QA
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    X_15 => C0,    -- 1CLKB
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    X_16 => open   -- Vcc
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);
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    E(0) <= C0;
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end architecture Test;

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