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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_70.vhd] - Blame information for rev 4

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1 3 david237 
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS70N: JK edge-triggered flipflop (Pinout A)    --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_70 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '0';
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    Period   : time           := 120 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_70 is
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    signal RS, CLK : std_logic;
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    signal J,  K   : std_logic;
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    signal JC, BC  : unsigned(5 downto 0);         -- Test stimuli
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    signal D,  E   : std_logic_vector(1 downto 0); -- Expected & actual results
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    SIM: process(CLK, RS) is
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        variable JK : std_logic_vector(1 downto 0);
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    begin
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        if    RS = '0' then
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            D(0) <= '0';
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        elsif rising_edge(CLK) then
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            JK := J & K;
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            case JK is
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                when "00"   => null;
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                when "01"   => D(0) <= '0';
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                when "10"   => D(0) <= '1';
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                when "11"   => D(0) <= not D(0);
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                when others => null;
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            end case;
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        end if;
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    end process;
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    D(1) <= not D(0);
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    J <= BC(0) and BC(1) and not BC(2);
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    K <= BC(3) and BC(4) and not BC(5);
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    -----------------------------------------------------------------------
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    -- Device Under Test...
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    -----------------------------------------------------------------------
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    DUT: SN74LS70N
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    port map(
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                   --
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    X_2  => RS,    -- CD\
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    X_3  => BC(0), -- J1
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    X_4  => BC(1), -- J2
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    X_5  => BC(2), -- J3\
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    X_6  => E(1),  -- Q\
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    X_7  => open,  -- GND
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    X_8  => E(0),  -- Q
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    X_9  => BC(5), -- K3\
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    X_10 => BC(3), -- K1
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    X_11 => BC(4), -- K2
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    X_12 => CLK,   -- CP
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    X_13 => '1',   -- SD\
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    X_14 => open   -- Vcc
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);
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end architecture Test;

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