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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_75.vhd] - Blame information for rev 6

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1 3 david237 
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- December, 2016.  Perth, Australia                                 --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS75N: 4-bit bistable latch                     --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_75 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '0';
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    Period   : time           := 100 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_75 is
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    signal CLK      : std_logic;
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    signal J, B     : unsigned(5 downto 0);         -- Test stimuli
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    signal D, E     : std_logic_vector(7 downto 0); -- Expected & actual results
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    signal S        : std_logic_vector(3 downto 0);
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    signal E12, E34 : std_logic;
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => J,
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        B    => B,
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        CLK  => CLK,
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        RS   => open,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(CLK) is
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    begin
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        if falling_edge(CLK) then
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            E12 <= J(4), '0' after 45 ns;
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            E34 <= J(5), '0' after 45 ns;
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        end if;
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    end process;
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    S <= (E34, E34, E12, E12);
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    G1: for i in 3 downto 0 generate
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    begin
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        process(S, J) is
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        begin
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            if S(i) = '1' then
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                D(i)   <= J(i);
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                D(i+4) <= not J(i);
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            end if;
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        end process;
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    end generate;
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    -----------------------------------------------------------------------
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    -- Device Under Test...
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    -----------------------------------------------------------------------
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    DUT: SN74LS75N
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    port map(
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    X_1  => E(4),  -- Q1\
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    X_2  => J(0),  -- D1
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    X_3  => J(1),  -- D2
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    X_4  => E34,   -- E34
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    X_5  => open,  -- Vcc
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    X_6  => J(2),  -- D3
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    X_7  => J(3),  -- D4
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    X_8  => E(7),  -- Q4\
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    X_9  => E(3),  -- Q4
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    X_10 => E(6),  -- Q3\
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    X_11 => E(2),  -- Q3
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    X_12 => open,  -- GND
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    X_13 => E12,   -- E12
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    X_14 => E(5),  -- Q2\
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    X_15 => E(1),  -- Q2
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    X_16 => E(0)   -- Q1
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);
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end architecture Test;

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