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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_80.vhd] - Blame information for rev 11

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN7480N: Gated full adder (Pinout A)                --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_80 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 100 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_80 is
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    signal JC, BC : unsigned(6 downto 0);         -- Test stimuli
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    signal D,  E  : std_logic_vector(2 downto 0); -- Expected & actual results
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => open,
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        RS   => open,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(BC) is
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        variable AX, BX, A, B : std_logic;
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        variable IP           : std_logic_vector(2 downto 0);
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    begin
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        AX := not (BC(3) and BC(4));
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        BX := not (BC(5) and BC(6));
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        A  := not (AX    and BC(1));
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        B  := not (BX    and BC(2));
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        IP := (BC(0), B, A);
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        case IP is
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            when "000"  => D(2) <= '1'; D(1) <= '1'; D(0) <= '0';
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            when "001"  => D(2) <= '1'; D(1) <= '0'; D(0) <= '1';
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            when "010"  => D(2) <= '1'; D(1) <= '0'; D(0) <= '1';
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            when "011"  => D(2) <= '0'; D(1) <= '1'; D(0) <= '0';
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            when "100"  => D(2) <= '0'; D(1) <= '0'; D(0) <= '1';
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            when "101"  => D(2) <= '1'; D(1) <= '1'; D(0) <= '0';
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            when "110"  => D(2) <= '1'; D(1) <= '1'; D(0) <= '0';
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            when "111"  => D(2) <= '0'; D(1) <= '0'; D(0) <= '1';
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            when others => D <= (others => 'X');
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        end case;
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN7480N
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    port map(
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                    -- BX
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    X_2  => BC(2),  -- BC
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    X_3  => BC(0),  -- CN
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    X_4  => E(2),   -- CNP1\
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    X_5  => E(0),   -- S
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    X_6  => E(1),   -- S\
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    X_7  => open,   -- GND
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    X_8  => BC(3),  -- A1
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    X_9  => BC(4),  -- A2
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                    -- AX
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    X_11 => BC(1),  -- AC
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    X_12 => BC(5),  -- B1
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    X_13 => BC(6),  -- B2
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    X_14 => open    -- Vcc
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);
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end architecture Test;

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