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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_85.vhd] - Blame information for rev 3

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS85N: 4-bit magnitude comparator               --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_85 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 100 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_85 is
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    signal JC, BC : unsigned(10 downto 0);        -- Test stimuli
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    signal D,  E  : std_logic_vector(2 downto 0); -- Expected & actual results
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    alias inLT is JC(10);
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    alias inEQ is JC( 9);
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    alias inGT is JC( 8);
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    alias A    is JC(7 downto 4);
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    alias B    is JC(3 downto 0);
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => open,
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        RS   => open,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(JC) is
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        variable LT, EQ, GT : std_logic;
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        variable INCOND     : std_logic_vector(2 downto 0);
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    begin
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        LT := '0';
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        EQ := '0';
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        GT := '0';
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        if    A < B then LT := '1';
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        elsif A > B then GT := '1';
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        else
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            INCOND := inGT & inLT & inEQ;
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            case INCOND is
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                when "100"  => GT := '1';
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                when "010"  => LT := '1';
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                when "000"  => GT := '1'; LT := '1';
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                when "110"  => null;
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                when others => EQ := '1';
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            end case;
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        end if;
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        D <= (LT, EQ, GT);
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74LS85N
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    port map(
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    X_1  => JC(3),  -- B3
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    X_2  => inLT,   -- IA<B
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    X_3  => inEQ,   -- IA=B
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    X_4  => inGT,   -- IA>B
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    X_5  => E(0),   -- OA>B
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    X_6  => E(1),   -- OA=B
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    X_7  => E(2),   -- OA<B
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    X_8  => open,   -- GND
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    X_9  => JC(0),  -- B0
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    X_10 => JC(4),  -- A0
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    X_11 => JC(1),  -- B1
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    X_12 => JC(5),  -- A1
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    X_13 => JC(6),  -- A2
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    X_14 => JC(2),  -- B2
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    X_15 => JC(7),  -- A3
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    X_16 => open    -- Vcc
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);
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end architecture Test;

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