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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_89.vhd] - Blame information for rev 3

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1 3 david237 
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS89N: 64-bit RAM (open collector)              --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_89 is     -- Top-level bench
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generic(
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    OC       : boolean        := true;
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 120 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_89 is
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    signal J, B      : unsigned(5 downto 0);         -- Unused
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    signal D, E      : std_logic_vector(3 downto 0); -- Expected & actual results
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    signal CLK, RS   : std_logic;
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    signal CS,  WR   : std_logic := '1';
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    signal AD        : TTLword   := (others => '0');
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    signal DI, Q, QQ : TTLquad;
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    signal CE, WE    : std_logic;
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    signal W         : std_logic;
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    signal Phase     : natural;
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => J,
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        B    => B,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate RAM-specific stimuli
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    -----------------------------------------------------------------------
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    CLKX: process(CLK, RS) is
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    begin
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        if RS = '0' then
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            Phase <=  0;
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            CS    <= '1';
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            WR    <= '1';
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        elsif rising_edge(CLK) then
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            case Phase is
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                when 0      => CS <= '0';             Phase <= 1;
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                when 1      =>             WR <=  W;  Phase <= 2;
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                when 2      =>             WR <= '1'; Phase <= 3;
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                when others => CS <= '1';  WR <= '1'; Phase <= 0;
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            end case;
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        end if;
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    end process;
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    UPDATE: process(CLK, RS) is
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        variable TD : unsigned(3 downto 0);
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    begin
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        if RS = '0' then
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            W  <= '0';
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            AD <= (others => '0');
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            TD := "0110";
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        elsif rising_edge(CLK) and Phase = 3 then
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            if AD = "1111" then
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                W <= not W;         -- Alternate read/write cycles
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            end if;
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            AD <= AD + 1;
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            TD := TD + 1;
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        end if;
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        for i in TD'range loop
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            DI(i+1) <= TD(i);
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        end loop;
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    end process;
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    CE <= WR and not CS;
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    WE <= not(WR or CS);
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    process(CE, WE, AD, DI) is
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        variable mem : TTLmem;      -- Testbench memory
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        variable adr : TTLaddr;
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        variable QI  : TTLquad;
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    begin
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        adr := TTL_to_integer(AD);
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        if WE'event and WE = '1' then
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            mem(adr) := not DI;     -- Data is output inverted
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        end if;
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        if CE = '1' then
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            QI := mem(adr);
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        else
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            QI := (others => 'Z');
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        end if;
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        if OC then
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            for i in Q'range loop
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                Q(i) <= TTL_OC(QI(i));
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            end loop;
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        else
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            Q <= QI;
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        end if;
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    end process;
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    D <= Q;
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    E <= QQ;
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    -----------------------------------------------------------------------
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    -- Device Under Test...
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    -----------------------------------------------------------------------
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    DUT: SN74LS89N
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    port map(
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        X_1  => AD(0),  -- A0
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        X_2  => CS,     -- CS\
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        X_3  => WR,     -- WE\
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        X_4  => DI(1),  -- D1
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        X_5  => QQ(1),  -- Q1\
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        X_6  => DI(2),  -- D2
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        X_7  => QQ(2),  -- Q2\
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        X_8  => open,   -- GND
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        X_9  => QQ(3),  -- Q3\
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        X_10 => DI(3),  -- D3
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        X_11 => QQ(4),  -- Q4\
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        X_12 => DI(4),  -- D4
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        X_13 => AD(3),  -- A3
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        X_14 => AD(2),  -- A2
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        X_15 => AD(1),  -- A1
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        X_16 => open    -- Vcc
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    );
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end architecture Test;

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