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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_91.vhd] - Blame information for rev 3

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-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS91AN: 8-bit shift register (Pinout A)         --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_91 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           := 120 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_91 is
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    signal RS     : std_logic;
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    signal CLK    : std_logic;
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    signal JC, BC : unsigned(2 downto 0);           -- Test stimuli
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    signal D,  E  : std_logic_vector(1 downto 0);   -- Expected & actual results
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    begin
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(CLK) is
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        variable SR : std_logic_vector(7 downto 0) := (others => 'U');
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    begin
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        if rising_edge(CLK) then
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            SR := SR(6 downto 0) & nand_reduce(std_logic_vector(JC(1 downto 0)));
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            D(0) <= SR(7);
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            D(1) <= not SR(7);
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74LS91AN
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    port map(
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                   -- 
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                   -- 
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                   -- 
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                   -- 
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    X_5  => open,  -- Vcc
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                   -- 
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                   -- 
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                   -- 
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    X_9  => CLK,   -- CP
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    X_10 => open,  -- GND
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    X_11 => JC(1), -- B
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    X_12 => JC(0), -- A
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    X_13 => E(0),  -- Q
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    X_14 => E(1)   -- Q\
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    );
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end architecture Test;

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