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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_95.vhd] - Blame information for rev 3

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1 3 david237
-----------------------------------------------------------------------
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-- Bipolar TTL models (VHDL)                                         --
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-- David R Brooks                                                    --
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-- June, 2016.  Perth, Australia                                     --
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-- Compliance: VHDL 2008                                             --
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-- Testbench for SN74LS95N: 4-bit right/left shift register          --
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-----------------------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_misc.all;
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    use ieee.numeric_std.all;
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    use work.LSTTL.all;
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    use work.TTLPrivate.all;
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entity Testbench_95 is     -- Top-level bench
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generic(
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    StimClk  : std_logic      := '1';
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    CheckClk : std_logic      := '1';
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    Period   : time           :=  50 ns;
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    Finish   : time           :=  20 us;
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    SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_95 is
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    signal RS               : std_logic;
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    signal CLK              : std_logic;
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    signal JC, BC           : unsigned(3 downto 0);           -- Test stimuli
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    signal D,  E            : std_logic_vector(3 downto 0);   -- Expected & actual results
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    signal P                : std_logic_vector(3 downto 0);
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    signal CP1, CP2, PE, DS : std_logic := '1';
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    begin
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    P  <= std_logic_vector(JC(3 downto 0));
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    DS <= JC(1);
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    process(CLK, RS) is     -- Generate special clocks, etc.
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        variable X   : unsigned(3 downto 0);
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        variable IPE, IC1, IC2 : std_logic := '1';
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    begin
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        if rising_edge(CLK) then
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            CP1 <= IC1;
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            CP2 <= IC2;
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            IC1 := '1';
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            IC2 := '1';
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            X   := BC(X'range);
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            if (X = "1000") or (RS = '0') then
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                IPE := '1';
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                IC2 := '0';  -- Load
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            else
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                IPE := '0';
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                IC1 := '0';  -- Shift
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            end if;
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        elsif falling_edge(CLK) then
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            CP1 <= '1';
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            CP2 <= '1';
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            PE  <= IPE;
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Standard testbench components
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    -----------------------------------------------------------------------
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    TB: TTLBench
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    generic map(
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        StimClk  => StimClk,
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        CheckClk => CheckClk,
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        Period   => Period,
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        Finish   => Finish,
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        SevLevel => SevLevel
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    )
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    port map(
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        J    => JC,
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        B    => BC,
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        CLK  => CLK,
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        RS   => RS,
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        D    => D,
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        E    => E
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    );
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    -----------------------------------------------------------------------
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    -- Generate expected results (with zero delays)
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    -----------------------------------------------------------------------
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    process(CP1, CP2) is
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    begin
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        if    falling_edge(CP1) and PE = '0' then
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            D <= D(2 downto 0) & DS;
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        elsif falling_edge(CP2) and PE = '1' then
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            D <= P;
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        end if;
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    end process;
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    -----------------------------------------------------------------------
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    -- Device Under Test...                        
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    -----------------------------------------------------------------------
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    DUT: SN74LS95N
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    port map(
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    X_1  => DS,  -- DS
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    X_2  => P(0),  -- P0
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    X_3  => P(1),  -- P1
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    X_4  => P(2),  -- P2
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    X_5  => P(3),  -- P3
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    X_6  => PE,  -- PE
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    X_7  => open,  -- GND
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    X_8  => CP2,  -- CP2\
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    X_9  => CP1,  -- CP1\
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    X_10 => E(3),  -- Q3
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    X_11 => E(2),  -- Q2
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    X_12 => E(1),  -- Q1
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    X_13 => E(0),  -- Q0
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    X_14 => open   -- Vcc
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    );
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end architecture Test;

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