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david237 |
-----------------------------------------------------------------------
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-- Basic SRAM models (VHDL) --
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-- David R Brooks --
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-- December, 2016. Perth, Australia --
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-- Compliance: VHDL 2008 --
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-- Testbench for CY7C1021: 64k x 16 SRAM (Cypress, 10 ns) --
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use work.TTLPrivate.all;
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use work.Memories.all;
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entity Testbench_CY7C1021 is -- Top-level bench
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generic(
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OC : boolean := false;
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StimClk : std_logic := '1';
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CheckClk : std_logic := '1';
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Period : time := 100 ns;
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Finish : time := 30 ms;
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SevLevel : severity_level := failure
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);
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end entity;
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architecture Test of Testbench_CY7C1021 is
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subtype TDATA is std_logic_vector(15 downto 0);
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subtype TADDR is unsigned(15 downto 0);
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constant KADTOP : natural := (2**(TADDR'high+1))-1;
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subtype TADNUM is natural range KADTOP downto 0;
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type TMEM is array(KADTOP downto 0) of TDATA;
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signal J, B : unsigned(10 downto 0); -- Unused
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signal D, E : TDATA; -- Expected & actual results
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signal CLK, RS : std_logic;
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signal CS, WR : std_logic := '1';
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signal AD : TADDR := (others => '0');
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signal DI : TDATA;
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signal W : std_logic;
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signal Phase : natural;
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signal OE : std_logic;
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signal BHE, BLE : std_logic;
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constant AD1 : TADDR := (others => '1');
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constant ID1 : unsigned(TDATA'range) := "0000000000000010";
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begin
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BHE <= '0';
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BLE <= '0';
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-----------------------------------------------------------------------
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-- Standard testbench components
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-----------------------------------------------------------------------
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TB: TTLBench
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generic map(
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StimClk => StimClk,
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CheckClk => CheckClk,
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Period => Period,
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Finish => Finish,
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SevLevel => SevLevel
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)
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port map(
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J => J,
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B => B,
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CLK => CLK,
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RS => RS,
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D => D,
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E => E
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);
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-----------------------------------------------------------------------
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-- Generate RAM-specific stimuli
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-----------------------------------------------------------------------
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CLKX: process(CLK, RS) is
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begin
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if RS = '0' then
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Phase <= 0;
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CS <= '1';
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WR <= '1';
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OE <= '1';
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elsif rising_edge(CLK) then
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case Phase is
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when 0 => CS <= '0'; Phase <= 1; OE <= '1';
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when 1 => WR <= W; Phase <= 2; OE <= not W;
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when 2 => WR <= '1'; Phase <= 3; OE <= '1';
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when others => CS <= '1'; WR <= '1'; Phase <= 0; OE <= '1';
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end case;
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end if;
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end process;
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UPDATE: process(CLK, RS) is
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variable TD : unsigned(TDATA'range);
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begin
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if RS = '0' then
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W <= '0';
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AD <= (others => '0');
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TD := ID1;
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elsif rising_edge(CLK) and Phase = 3 then
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if AD = AD1 then
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W <= not W; -- Alternate read/write cycles
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end if;
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AD <= AD + 1;
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TD := TD + 1;
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end if;
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DI <= TDATA(TD);
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end process;
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-----------------------------------------------------------------------
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-- Generate expected results (with zero delays)
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-----------------------------------------------------------------------
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process(all) is
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variable mem : TMEM; -- Testbench memory
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variable adr : TADNUM;
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variable QI : TDATA;
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begin
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D <= E; -- Default, if not active
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if CS = '0' then -- Device active
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adr := TTL_to_integer(AD);
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if rising_edge(WR) then -- Rising (ie trailing) edge
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mem(adr) := DI;
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end if;
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if OE = '0' then -- Reading
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QI := mem(adr);
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else
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QI := (others => 'Z');
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end if;
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if OC then -- Simulate open collector
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for i in D'range loop
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D(i) <= TTL_OC(QI(i));
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end loop;
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else
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D <= QI;
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end if;
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end if;
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end process;
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process(CLK) is -- During writes, mimic the data
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begin
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if falling_edge(CLK) then
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if W = '0' then
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case Phase is
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when 1 | 2 => D <= E;
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when others => D <= (others => 'Z');
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end case;
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end if;
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end if;
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end process;
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E <= DI when (W = '0') and (Phase = 1 or Phase = 2) else (others => 'Z');
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-----------------------------------------------------------------------
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-- Device Under Test...
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-----------------------------------------------------------------------
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DUT: CY7C1021
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generic map(
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fnevn => "", -- Name of even-byte initialisation file (if any)
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fnodd => "" -- Name of odd-byte initialisation file (if any)
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)
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port map(
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X_1 => AD(4), -- A4
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X_2 => AD(3), -- A3
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X_3 => AD(2), -- A2
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X_4 => AD(1), -- A1
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X_5 => AD(0), -- A0
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X_6 => CS, -- CE\
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X_7 => E(0), -- IO0
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X_8 => E(1), -- IO1
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X_9 => E(2), -- IO2
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X_10 => E(3), -- IO3
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X_11 => open, -- Vcc
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X_12 => open, -- GND
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X_13 => E(4), -- IO4
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X_14 => E(5), -- IO5
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X_15 => E(6), -- IO6
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X_16 => E(7), -- IO7
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X_17 => WR, -- WE\
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X_18 => AD(15), -- A15
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X_19 => AD(14), -- A14
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X_20 => AD(13), -- A13
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X_21 => AD(12), -- A12
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-- X_22
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-- X_23
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X_24 => AD(11), -- A11
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X_25 => AD(10), -- A10
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X_26 => AD(9), -- A9
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X_27 => AD(8), -- A8
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-- X_28
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X_29 => E(8), -- IO8
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X_30 => E(9), -- IO9
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X_31 => E(10), -- IO10
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X_32 => E(11), -- IO11
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X_33 => open, -- VCC
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X_34 => open, -- GND
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X_35 => E(12), -- IO12
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X_36 => E(13), -- IO13
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X_37 => E(14), -- IO14
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X_38 => E(15), -- IO15
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X_39 => BLE, -- BLE\
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X_40 => BHE, -- BHE\
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X_41 => OE, -- OE\
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X_42 => AD(7), -- A7
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X_43 => AD(6), -- A6
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X_44 => AD(5) -- A5
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);
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end architecture Test;
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