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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_HM6116.vhd] - Blame information for rev 5

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-----------------------------------------------------------------------
-- Basic SRAM models (VHDL)                                          --
-- David R Brooks                                                    --
-- December, 2016.  Perth, Australia                                 --
-- Compliance: VHDL 2008                                             --
-- Testbench for HM6116: 2k x 8 SRAM                                 --
-----------------------------------------------------------------------
 
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_misc.all;
    use ieee.numeric_std.all;
 
    use work.TTLPrivate.all;
    use work.Memories.all;
 
entity Testbench_HM6116 is     -- Top-level bench
generic(
    OC       : boolean        := false;
    StimClk  : std_logic      := '1';
    CheckClk : std_logic      := '1';
    Period   : time           := 100 ns;
    Finish   : time           :=   2 ms;
    SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_HM6116 is
    subtype  TDATA   is std_logic_vector(7 downto 0);
    subtype  TADDR   is unsigned(10 downto 0);
    constant KADTOP  :  natural := (2**(TADDR'high+1))-1;
    subtype  TADNUM  is natural range KADTOP downto 0;
    type     TMEM    is array(KADTOP downto 0) of TDATA;
 
    signal J, B      : unsigned(10 downto 0);           -- Unused
    signal D, E      : TDATA;                           -- Expected & actual results
    signal CLK, RS   : std_logic;
    signal CS,  WR   : std_logic := '1';
    signal AD        : TADDR := (others => '0');
    signal DI        : TDATA;
    signal W         : std_logic;
    signal Phase     : natural;
    signal OE        : std_logic;
 
    constant AD1     : TADDR := (others => '1');
    constant ID1     : unsigned(TDATA'range) := "00000010";
 
    begin
 
    -----------------------------------------------------------------------
    -- Standard testbench components
    -----------------------------------------------------------------------
    TB: TTLBench
    generic map(
        StimClk  => StimClk,
        CheckClk => CheckClk,
        Period   => Period,
        Finish   => Finish,
        SevLevel => SevLevel
    )
    port map(
        J    => J,
        B    => B,
        CLK  => CLK,
        RS   => RS,
        D    => D,
        E    => E
    );
 
    -----------------------------------------------------------------------
    -- Generate RAM-specific stimuli
    -----------------------------------------------------------------------
    CLKX: process(CLK, RS) is
    begin
        if RS = '0' then
            Phase <=  0;
            CS    <= '1';
            WR    <= '1';
            OE    <= '1';
        elsif rising_edge(CLK) then
            case Phase is
                when 0      => CS <= '0';             Phase <= 1;   OE <= '1';
                when 1      =>             WR <=  W;  Phase <= 2;   OE <= not W;
                when 2      =>             WR <= '1'; Phase <= 3;   OE <= '1';
                when others => CS <= '1';  WR <= '1'; Phase <= 0;   OE <= '1';
            end case;
        end if;
    end process;
 
    UPDATE: process(CLK, RS) is
        variable TD : unsigned(TDATA'range);
    begin
        if RS = '0' then
            W  <= '0';
            AD <= (others => '0');
            TD := ID1;
        elsif rising_edge(CLK) and Phase = 3 then
            if AD = AD1 then
                W <= not W;         -- Alternate read/write cycles
            end if;
            AD <= AD + 1;
            TD := TD + 1;
        end if;
        DI <= TDATA(TD);
    end process;
 
    -----------------------------------------------------------------------
    -- Generate expected results (with zero delays)
    -----------------------------------------------------------------------    
    process(all) is
        variable mem    : TMEM;             -- Testbench memory
        variable adr    : TADNUM;
        variable QI     : TDATA;
    begin
        D <= E;                             -- Default, if not active
 
        if CS = '0' then                    -- Device active
            adr := TTL_to_integer(AD);
            if rising_edge(WR) then         -- Rising (ie trailing) edge
                mem(adr) := DI;
            end if;
 
            if OE = '0' then                -- Reading
                QI := mem(adr);
            else
                QI := (others => 'Z');
            end if;
 
            if OC then                      -- Simulate open collector
                for i in D'range loop
                    D(i) <= TTL_OC(QI(i));
                end loop;
            else
                D <= QI;
            end if;
        end if;
    end process;
 
    process(CLK) is                         -- During writes, mimic the data
    begin
        if falling_edge(CLK) then
            if W = '0' then
                case Phase is
                    when 1 | 2  => D <= E;
                    when others => D <= (others => 'Z');
                end case;
            end if;
        end if;
    end process;
 
    E <= DI when (W = '0') and (Phase = 1 or Phase = 2) else (others => 'Z');
 
    -----------------------------------------------------------------------
    -- Device Under Test...                        
    -----------------------------------------------------------------------
    DUT: HM6116
generic map(
    fname  => ""           -- Name of initialisation file (if any)
)
port map(
    X_1  => AD(7),  -- A7
    X_2  => AD(6),  -- A6
    X_3  => AD(5),  -- A5
    X_4  => AD(4),  -- A4
    X_5  => AD(3),  -- A3
    X_6  => AD(2),  -- A2
    X_7  => AD(1),  -- A1
    X_8  => AD(0),  -- A0
    X_9  => E(0),   -- IO0
    X_10 => E(1),   -- IO1
    X_11 => E(2),   -- IO2
    X_12 => open,   -- GND
    X_13 => E(3),   -- IO3
    X_14 => E(4),   -- IO4 
    X_15 => E(5),   -- IO5
    X_16 => E(6),   -- IO6
    X_17 => E(7),   -- IO7
    X_18 => CS,     -- CS\
    X_19 => AD(10), -- A10
    X_20 => OE,     -- OE\
    X_21 => WR,     -- WE\
    X_22 => AD(9),  -- A9
    X_23 => AD(8),  -- A8
    X_24 => open    -- Vcc
);
end architecture Test;

Line No.	Rev	Author	Line
1	3	david237	`-----------------------------------------------------------------------`
2			`-- Basic SRAM models (VHDL) --`
3			`-- David R Brooks --`
4			`-- December, 2016. Perth, Australia --`
5			`-- Compliance: VHDL 2008 --`
6			`-- Testbench for HM6116: 2k x 8 SRAM --`
7			`-----------------------------------------------------------------------`
8
9			`library ieee;`
10			`use ieee.std_logic_1164.all;`
11			`use ieee.std_logic_misc.all;`
12			`use ieee.numeric_std.all;`
13
14			`use work.TTLPrivate.all;`
15			`use work.Memories.all;`
16
17			`entity Testbench_HM6116 is -- Top-level bench`
18			`generic(`
19			`OC : boolean := false;`
20			`StimClk : std_logic := '1';`
21			`CheckClk : std_logic := '1';`
22			`Period : time := 100 ns;`
23			`Finish : time := 2 ms;`
24			`SevLevel : severity_level := failure`
25			`);`
26			`end entity;`
27
28			`architecture Test of Testbench_HM6116 is`
29			`subtype TDATA is std_logic_vector(7 downto 0);`
30			`subtype TADDR is unsigned(10 downto 0);`
31			`constant KADTOP : natural := (2**(TADDR'high+1))-1;`
32			`subtype TADNUM is natural range KADTOP downto 0;`
33			`type TMEM is array(KADTOP downto 0) of TDATA;`
34
35			`signal J, B : unsigned(10 downto 0); -- Unused`
36			`signal D, E : TDATA; -- Expected & actual results`
37			`signal CLK, RS : std_logic;`
38			`signal CS, WR : std_logic := '1';`
39			`signal AD : TADDR := (others => '0');`
40			`signal DI : TDATA;`
41			`signal W : std_logic;`
42			`signal Phase : natural;`
43			`signal OE : std_logic;`
44
45			`constant AD1 : TADDR := (others => '1');`
46			`constant ID1 : unsigned(TDATA'range) := "00000010";`
47
48			`begin`
49
50			`-----------------------------------------------------------------------`
51			`-- Standard testbench components`
52			`-----------------------------------------------------------------------`
53			`TB: TTLBench`
54			`generic map(`
55			`StimClk => StimClk,`
56			`CheckClk => CheckClk,`
57			`Period => Period,`
58			`Finish => Finish,`
59			`SevLevel => SevLevel`
60			`)`
61			`port map(`
62			`J => J,`
63			`B => B,`
64			`CLK => CLK,`
65			`RS => RS,`
66			`D => D,`
67			`E => E`
68			`);`
69
70			`-----------------------------------------------------------------------`
71			`-- Generate RAM-specific stimuli`
72			`-----------------------------------------------------------------------`
73			`CLKX: process(CLK, RS) is`
74			`begin`
75			`if RS = '0' then`
76			`Phase <= 0;`
77			`CS <= '1';`
78			`WR <= '1';`
79			`OE <= '1';`
80			`elsif rising_edge(CLK) then`
81			`case Phase is`
82			`when 0 => CS <= '0'; Phase <= 1; OE <= '1';`
83			`when 1 => WR <= W; Phase <= 2; OE <= not W;`
84			`when 2 => WR <= '1'; Phase <= 3; OE <= '1';`
85			`when others => CS <= '1'; WR <= '1'; Phase <= 0; OE <= '1';`
86			`end case;`
87			`end if;`
88			`end process;`
89
90			`UPDATE: process(CLK, RS) is`
91			`variable TD : unsigned(TDATA'range);`
92			`begin`
93			`if RS = '0' then`
94			`W <= '0';`
95			`AD <= (others => '0');`
96			`TD := ID1;`
97			`elsif rising_edge(CLK) and Phase = 3 then`
98			`if AD = AD1 then`
99			`W <= not W; -- Alternate read/write cycles`
100			`end if;`
101			`AD <= AD + 1;`
102			`TD := TD + 1;`
103			`end if;`
104			`DI <= TDATA(TD);`
105			`end process;`
106
107			`-----------------------------------------------------------------------`
108			`-- Generate expected results (with zero delays)`
109			`-----------------------------------------------------------------------`
110			`process(all) is`
111			`variable mem : TMEM; -- Testbench memory`
112			`variable adr : TADNUM;`
113			`variable QI : TDATA;`
114			`begin`
115			`D <= E; -- Default, if not active`
116
117			`if CS = '0' then -- Device active`
118			`adr := TTL_to_integer(AD);`
119			`if rising_edge(WR) then -- Rising (ie trailing) edge`
120			`mem(adr) := DI;`
121			`end if;`
122
123			`if OE = '0' then -- Reading`
124			`QI := mem(adr);`
125			`else`
126			`QI := (others => 'Z');`
127			`end if;`
128
129			`if OC then -- Simulate open collector`
130			`for i in D'range loop`
131			`D(i) <= TTL_OC(QI(i));`
132			`end loop;`
133			`else`
134			`D <= QI;`
135			`end if;`
136			`end if;`
137			`end process;`
138
139			`process(CLK) is -- During writes, mimic the data`
140			`begin`
141			`if falling_edge(CLK) then`
142			`if W = '0' then`
143			`case Phase is`
144			`when 1 \| 2 => D <= E;`
145			`when others => D <= (others => 'Z');`
146			`end case;`
147			`end if;`
148			`end if;`
149			`end process;`
150
151			`E <= DI when (W = '0') and (Phase = 1 or Phase = 2) else (others => 'Z');`
152
153			`-----------------------------------------------------------------------`
154			`-- Device Under Test...`
155			`-----------------------------------------------------------------------`
156			`DUT: HM6116`
157			`generic map(`
158			`fname => "" -- Name of initialisation file (if any)`
159			`)`
160			`port map(`
161			`X_1 => AD(7), -- A7`
162			`X_2 => AD(6), -- A6`
163			`X_3 => AD(5), -- A5`
164			`X_4 => AD(4), -- A4`
165			`X_5 => AD(3), -- A3`
166			`X_6 => AD(2), -- A2`
167			`X_7 => AD(1), -- A1`
168			`X_8 => AD(0), -- A0`
169			`X_9 => E(0), -- IO0`
170			`X_10 => E(1), -- IO1`
171			`X_11 => E(2), -- IO2`
172			`X_12 => open, -- GND`
173			`X_13 => E(3), -- IO3`
174			`X_14 => E(4), -- IO4`
175			`X_15 => E(5), -- IO5`
176			`X_16 => E(6), -- IO6`
177			`X_17 => E(7), -- IO7`
178			`X_18 => CS, -- CS\`
179			`X_19 => AD(10), -- A10`
180			`X_20 => OE, -- OE\`
181			`X_21 => WR, -- WE\`
182			`X_22 => AD(9), -- A9`
183			`X_23 => AD(8), -- A8`
184			`X_24 => open -- Vcc`
185			`);`
186			`end architecture Test;`

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[/] [ttl_library/] [trunk/] [Testbench/] [Testbench_HM6116.vhd] - Blame information for rev 5