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[/] [turbo8051/] [trunk/] [fpga/] [altera/] [summary/] [turbo8051.tan.summary] - Blame information for rev 34

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Line No. Rev Author Line
1 34 dinesha 
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2 
Timing Analyzer Summary
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4 
 
5 
Type           : Worst-case tsu
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Slack          : N/A
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Required Time  : None
8 
Actual Time    : 26.898 ns
9 
From           : wb_xrom_ack
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To             : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4]
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From Clock     : --
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To Clock       : xtal_clk
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Failed Paths   : 0
14 
 
15 
Type           : Worst-case tco
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Slack          : N/A
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Required Time  : None
18 
Actual Time    : 19.423 ns
19 
From           : oc8051_top:u_8051_core|oc8051_sfr:oc8051_sfr1|wait_data
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To             : wb_xram_adr[14]
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From Clock     : xtal_clk
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To Clock       : --
23 
Failed Paths   : 0
24 
 
25 
Type           : Worst-case tpd
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Slack          : N/A
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Required Time  : None
28 
Actual Time    : 16.411 ns
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From           : wb_xram_rdata[5]
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To             : ext_reg_rdata[13]
31 
From Clock     : --
32 
To Clock       : --
33 
Failed Paths   : 0
34 
 
35 
Type           : Worst-case th
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Slack          : N/A
37 
Required Time  : None
38 
Actual Time    : -0.037 ns
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From           : ext_reg_tid[1]
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To             : wb_crossbar:u_wb_crossbar|master_mx_id[2][1]
41 
From Clock     : --
42 
To Clock       : xtal_clk
43 
Failed Paths   : 0
44 
 
45 
Type           : Worst-case Minimum Pulse Width Requirement (Low)
46 
Slack          : -0.564 ns
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Required Time  : 2.564 ns
48 
Actual Time    : 2.000 ns
49 
From           : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
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To             : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_reg
51 
From Clock     : --
52 
To Clock       : --
53 
Failed Paths   : 58
54 
 
55 
Type           : Worst-case Minimum Pulse Width Requirement (High)
56 
Slack          : -0.564 ns
57 
Required Time  : 2.564 ns
58 
Actual Time    : 2.000 ns
59 
From           : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
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To             : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_reg
61 
From Clock     : --
62 
To Clock       : --
63 
Failed Paths   : 58
64 
 
65 
Type           : Clock Setup: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0'
66 
Slack          : -21.494 ns
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Required Time  : 250.00 MHz ( period = 4.000 ns )
68 
Actual Time    : 39.22 MHz ( period = 25.494 ns )
69 
From           : oc8051_top:u_8051_core|oc8051_decoder:oc8051_decoder1|altsyncram:WideOr30_rtl_2|altsyncram_ia01:auto_generated|ram_block1a0~porta_address_reg7
70 
To             : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4]
71 
From Clock     : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
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To Clock       : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
73 
Failed Paths   : 310109
74 
 
75 
Type           : Clock Setup: 'xtal_clk'
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Slack          : 36.125 ns
77 
Required Time  : 25.00 MHz ( period = 40.000 ns )
78 
Actual Time    : 258.06 MHz ( period = 3.875 ns )
79 
From           : clkgen:u_clkgen|pll_count[0]
80 
To             : clkgen:u_clkgen|pll_count[11]
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From Clock     : xtal_clk
82 
To Clock       : xtal_clk
83 
Failed Paths   : 0
84 
 
85 
Type           : Clock Hold: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0'
86 
Slack          : 0.460 ns
87 
Required Time  : 250.00 MHz ( period = 4.000 ns )
88 
Actual Time    : N/A
89 
From           : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_n
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To             : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_n
91 
From Clock     : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
92 
To Clock       : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0
93 
Failed Paths   : 0
94 
 
95 
Type           : Clock Hold: 'xtal_clk'
96 
Slack          : 0.460 ns
97 
Required Time  : 25.00 MHz ( period = 40.000 ns )
98 
Actual Time    : N/A
99 
From           : clkgen:u_clkgen|pll_count[6]
100 
To             : clkgen:u_clkgen|pll_count[6]
101 
From Clock     : xtal_clk
102 
To Clock       : xtal_clk
103 
Failed Paths   : 0
104 
 
105 
Type           : Other violations (see messages)
106 
Slack          :
107 
Required Time  :
108 
Actual Time    :
109 
From           :
110 
To             :
111 
From Clock     :
112 
To Clock       :
113 
Failed Paths   : 1
114 
 
115 
Type           : Total number of failed paths
116 
Slack          :
117 
Required Time  :
118 
Actual Time    :
119 
From           :
120 
To             :
121 
From Clock     :
122 
To Clock       :
123 
Failed Paths   : 310226
124 
 
125 
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