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dinesha |
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.0 Build 132 02/25/2009 SJ Full Version
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# Date created = 16:06:19 March 15, 2011
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# turbo8051_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C15AF484A7
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set_global_assignment -name TOP_LEVEL_ENTITY turbo8051
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:06:19 MARCH 15, 2011"
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set_global_assignment -name LAST_QUARTUS_VERSION 9.0
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
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set_global_assignment -name SEARCH_PATH ../../rtl/lib
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set_global_assignment -name SEARCH_PATH ../../rtl/8051
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name VERILOG_FILE ../../models/altera/altera_stargate_pll.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_wr_mem2mem.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/clk_ctl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/dble_reg.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/double_sync_high.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/double_sync_low.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/dpath_ctrl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/registers.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/sfifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/stat_counter.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/toggle_sync.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_crossbar.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_interface.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_rd_mem2mem.v
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set_global_assignment -name VERILOG_FILE ../../rtl/lib/async_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/core/core.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/top/g_mac_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_tx_fsm.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_deferral.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_tx_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_rx_fsm.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_cfg_mgmt.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/s2f_sync.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_md_intf.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_ad_fltr.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_deferral_rx.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_rx_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_mii_intf.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_mac_core.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/crc32/g_rx_crc32.v
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set_global_assignment -name VERILOG_FILE ../../rtl/gmac/crc32/g_tx_crc32.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_core.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_ctl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_if.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_cfg.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_rxfsm.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_txfsm.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_core.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_cfg.v
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set_global_assignment -name VERILOG_FILE ../../rtl/clkgen/clkgen.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_alu_src_sel.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_alu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_decoder.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_divide.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_multiply.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_memory_interface.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ram_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_acc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_comp.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_sp.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_dptr.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_cy_select.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_psw.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_indi_addr.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ports.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_b_register.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_uart.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_int.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_tc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_tc2.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_sfr.v
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set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ram_256x8_two_bist.v
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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