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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_int.v] - Blame information for rev 76

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores interrupt control module                         ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
//// http://www.opencores.org/cores/turb08051/                    ////
////                                                              ////
////  Description                                                 ////
////   contains sfr's: tcon, ip, ie;                              ////
////   interrupt handling                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Jaka Simsic, jakas@opencores.org                      ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2003/06/03 17:12:05  simont
// fix some bugs.
//
// Revision 1.8  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.7  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.6  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.5  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "top_defines.v"
 
 
 
module oc8051_int (clk, rst,
        wr_addr,
        data_in, bit_in,
        wr, wr_bit,
//timer interrupts
        tf0, tf1, t2_int,
        tr0, tr1,
//external interrupts
        ie0, ie1,
//uart interrupts
        uart_int,
//to cpu
        intr, reti, int_vec, ack,
//registers
        ie, tcon, ip);
 
input [7:0] wr_addr, data_in;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr;
output [7:0] int_vec,
             ie,
             tcon,
             ip;
 
reg [7:0] ip, ie, int_vec;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;
 
//
// isrc         processing interrupt sources
// int_dept
wire [2:0] isrc_cur;
reg [2:0] isrc [1:0];
reg [1:0] int_dept;
wire [1:0] int_dept_1;
reg int_proc;
reg [1:0] int_lev [1:0];
wire cur_lev;
 
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
assign int_dept_1 = int_dept - 2'b01;
assign cur_lev = int_lev[int_dept_1];
 
//
// contains witch level of interrupts is running
//reg [1:0] int_levl, int_levl_w;
 
//
// int_ln       waiting interrupts on level n
// ip_ln        interrupts on level n
// int_src      interrupt sources
wire [5:0] int_l0, int_l1;
wire [5:0] ip_l0, ip_l1;
wire [5:0] int_src;
wire il0, il1;
 
 
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
 
//
//interrupt priority
assign ip_l0 = ~ip[5:0];
assign ip_l1 = ip[5:0];
 
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
 
//
// waiting interrupts
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
assign il0 = |int_l0;
assign il1 = |int_l1;
 
//
// TCON
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
 
//
// IP
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
   ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
   ip[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// IE
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
   ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
   ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0]) /* synopsys full_case parallel_case */
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
//
// interrupt processing
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    int_vec <= #1 8'h00;
    int_dept <= #1 2'b0;
    isrc[0] <= #1 3'h0;
    isrc[1] <= #1 3'h0;
    int_proc <= #1 1'b0;
    int_lev[0] <= #1 1'b0;
    int_lev[1] <= #1 1'b0;
  end else if (reti & int_proc) begin  // return from interrupt
   if (int_dept==2'b01)
     int_proc <= #1 1'b0;
   int_dept <= #1 int_dept - 2'b01;
  end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin  // interrupt on level 1
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l1[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 
 end else if ((ie[7]) & !int_proc & il0) begin  // interrupt on level 0
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
   int_dept <= #1 2'b01;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l0[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    tf0_buff <= #1 1'b0;
    tf1_buff <= #1 1'b0;
    ie0_buff <= #1 1'b0;
    ie1_buff <= #1 1'b0;
  end else begin
    tf0_buff <= #1 tf0;
    tf1_buff <= #1 tf1;
    ie0_buff <= #1 ie0;
    ie1_buff <= #1 ie1;
  end
 
endmodule

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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_int.v] - Blame information for rev 76

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores interrupt control module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6	76	dinesha	`//// http://www.opencores.org/cores/turb08051/ ////`
7	2	dinesha	`//// ////`
8			`//// Description ////`
9			`//// contains sfr's: tcon, ip, ie; ////`
10			`//// interrupt handling ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Teran, simont@opencores.org ////`
17			`//// - Jaka Simsic, jakas@opencores.org ////`
18	76	dinesha	`//// - Dinesh Annayya, dinesha@opencores.org ////`
19	2	dinesha	`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`// Revision 1.9 2003/06/03 17:12:05 simont`
51			`// fix some bugs.`
52			`//`
53			`// Revision 1.8 2003/04/07 14:58:02 simont`
54			`// change sfr's interface.`
55			`//`
56			`// Revision 1.7 2003/03/28 17:45:57 simont`
57			`// change module name.`
58			`//`
59			`// Revision 1.6 2003/01/13 14:14:41 simont`
60			`// replace some modules`
61			`//`
62			`// Revision 1.5 2002/09/30 17:33:59 simont`
63			`// prepared header`
64			`//`
65			`//`
66
67
68	76	dinesha	`include "top_defines.v"
69	2	dinesha
70
71
72			`module oc8051_int (clk, rst,`
73			`wr_addr,`
74			`data_in, bit_in,`
75			`wr, wr_bit,`
76			`//timer interrupts`
77			`tf0, tf1, t2_int,`
78			`tr0, tr1,`
79			`//external interrupts`
80			`ie0, ie1,`
81			`//uart interrupts`
82			`uart_int,`
83			`//to cpu`
84			`intr, reti, int_vec, ack,`
85			`//registers`
86			`ie, tcon, ip);`
87
88			`input [7:0] wr_addr, data_in;`
89			`input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;`
90
91			`output tr0, tr1, intr;`
92			`output [7:0] int_vec,`
93			`ie,`
94			`tcon,`
95			`ip;`
96
97			`reg [7:0] ip, ie, int_vec;`
98
99			`reg [3:0] tcon_s;`
100			`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;`
101
102			`//`
103			`// isrc processing interrupt sources`
104			`// int_dept`
105			`wire [2:0] isrc_cur;`
106			`reg [2:0] isrc [1:0];`
107			`reg [1:0] int_dept;`
108			`wire [1:0] int_dept_1;`
109			`reg int_proc;`
110			`reg [1:0] int_lev [1:0];`
111			`wire cur_lev;`
112
113			`assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;`
114			`assign int_dept_1 = int_dept - 2'b01;`
115			`assign cur_lev = int_lev[int_dept_1];`
116
117			`//`
118			`// contains witch level of interrupts is running`
119			`//reg [1:0] int_levl, int_levl_w;`
120
121			`//`
122			`// int_ln waiting interrupts on level n`
123			`// ip_ln interrupts on level n`
124			`// int_src interrupt sources`
125			`wire [5:0] int_l0, int_l1;`
126			`wire [5:0] ip_l0, ip_l1;`
127			`wire [5:0] int_src;`
128			`wire il0, il1;`
129
130
131			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
132
133			`//`
134			`//interrupt priority`
135			`assign ip_l0 = ~ip[5:0];`
136			`assign ip_l1 = ip[5:0];`
137
138			`assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
139
140			`//`
141			`// waiting interrupts`
142			`assign int_l0 = ip_l0 & {ie[5:0]} & int_src;`
143			`assign int_l1 = ip_l1 & {ie[5:0]} & int_src;`
144			`assign il0 = \|int_l0;`
145			`assign il1 = \|int_l1;`
146
147			`//`
148			`// TCON`
149			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
150			`assign tr0 = tcon_s[2];`
151			`assign tr1 = tcon_s[3];`
152			`assign intr = \|int_vec;`
153
154
155			`//`
156			`// IP`
157			`always @(posedge clk or posedge rst)`
158			`begin`
159			`if (rst) begin`
160			ip <=#1 `OC8051_RST_IP;
161			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
162			`ip <= #1 data_in;`
163			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
164			`ip[wr_addr[2:0]] <= #1 bit_in;`
165			`end`
166
167			`//`
168			`// IE`
169			`always @(posedge clk or posedge rst)`
170			`begin`
171			`if (rst) begin`
172			ie <=#1 `OC8051_RST_IE;
173			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
174			`ie <= #1 data_in;`
175			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
176			`ie[wr_addr[2:0]] <= #1 bit_in;`
177			`end`
178
179			`//`
180			`// tcon_s`
181			`//`
182			`always @(posedge clk or posedge rst)`
183			`begin`
184			`if (rst) begin`
185			`tcon_s <=#1 4'b0000;`
186			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
187			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
188			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
189			`case (wr_addr[2:0]) /* synopsys full_case parallel_case */`
190			`3'b000: tcon_s[0] <= #1 bit_in;`
191			`3'b010: tcon_s[1] <= #1 bit_in;`
192			`3'b100: tcon_s[2] <= #1 bit_in;`
193			`3'b110: tcon_s[3] <= #1 bit_in;`
194			`endcase`
195			`end`
196			`end`
197
198			`//`
199			`// tf1 (tmod.7)`
200			`//`
201			`always @(posedge clk or posedge rst)`
202			`begin`
203			`if (rst) begin`
204			`tcon_tf1 <=#1 1'b0;`
205			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
206			`tcon_tf1 <= #1 data_in[7];`
207			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
208			`tcon_tf1 <= #1 bit_in;`
209			`end else if (!(tf1_buff) & (tf1)) begin`
210			`tcon_tf1 <= #1 1'b1;`
211			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
212			`tcon_tf1 <= #1 1'b0;`
213			`end`
214			`end`
215
216			`//`
217			`// tf0 (tmod.5)`
218			`//`
219			`always @(posedge clk or posedge rst)`
220			`begin`
221			`if (rst) begin`
222			`tcon_tf0 <=#1 1'b0;`
223			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
224			`tcon_tf0 <= #1 data_in[5];`
225			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
226			`tcon_tf0 <= #1 bit_in;`
227			`end else if (!(tf0_buff) & (tf0)) begin`
228			`tcon_tf0 <= #1 1'b1;`
229			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
230			`tcon_tf0 <= #1 1'b0;`
231			`end`
232			`end`
233
234
235			`//`
236			`// ie0 (tmod.1)`
237			`//`
238			`always @(posedge clk or posedge rst)`
239			`begin`
240			`if (rst) begin`
241			`tcon_ie0 <=#1 1'b0;`
242			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
243			`tcon_ie0 <= #1 data_in[1];`
244			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
245			`tcon_ie0 <= #1 bit_in;`
246			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
247			`tcon_ie0 <= #1 1'b1;`
248			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
249			`tcon_ie0 <= #1 1'b0;`
250			`end else if (!(tcon_s[0]) & (ie0)) begin`
251			`tcon_ie0 <= #1 1'b0;`
252			`end`
253			`end`
254
255
256			`//`
257			`// ie1 (tmod.3)`
258			`//`
259			`always @(posedge clk or posedge rst)`
260			`begin`
261			`if (rst) begin`
262			`tcon_ie1 <=#1 1'b0;`
263			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
264			`tcon_ie1 <= #1 data_in[3];`
265			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
266			`tcon_ie1 <= #1 bit_in;`
267			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
268			`tcon_ie1 <= #1 1'b1;`
269			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
270			`tcon_ie1 <= #1 1'b0;`
271			`end else if (!(tcon_s[1]) & (ie1)) begin`
272			`tcon_ie1 <= #1 1'b0;`
273			`end`
274			`end`
275
276			`//`
277			`// interrupt processing`
278			`always @(posedge clk or posedge rst)`
279			`begin`
280			`if (rst) begin`
281			`int_vec <= #1 8'h00;`
282			`int_dept <= #1 2'b0;`
283			`isrc[0] <= #1 3'h0;`
284			`isrc[1] <= #1 3'h0;`
285			`int_proc <= #1 1'b0;`
286			`int_lev[0] <= #1 1'b0;`
287			`int_lev[1] <= #1 1'b0;`
288			`end else if (reti & int_proc) begin // return from interrupt`
289			`if (int_dept==2'b01)`
290			`int_proc <= #1 1'b0;`
291			`int_dept <= #1 int_dept - 2'b01;`
292			`end else if (((ie[7]) & (!cur_lev) \|\| !int_proc) & il1) begin // interrupt on level 1`
293			`int_proc <= #1 1'b1;`
294			int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
295			`int_dept <= #1 int_dept + 2'b01;`
296			`if (int_l1[0]) begin`
297			int_vec <= #1 `OC8051_INT_X0;
298			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
299			`end else if (int_l1[1]) begin`
300			int_vec <= #1 `OC8051_INT_T0;
301			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
302			`end else if (int_l1[2]) begin`
303			int_vec <= #1 `OC8051_INT_X1;
304			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
305			`end else if (int_l1[3]) begin`
306			int_vec <= #1 `OC8051_INT_T1;
307			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
308			`end else if (int_l1[4]) begin`
309			int_vec <= #1 `OC8051_INT_UART;
310			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
311			`end else if (int_l1[5]) begin`
312			int_vec <= #1 `OC8051_INT_T2;
313			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
314			`end`
315
316			`end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0`
317			`int_proc <= #1 1'b1;`
318			int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
319			`int_dept <= #1 2'b01;`
320			`if (int_l0[0]) begin`
321			int_vec <= #1 `OC8051_INT_X0;
322			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
323			`end else if (int_l0[1]) begin`
324			int_vec <= #1 `OC8051_INT_T0;
325			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
326			`end else if (int_l0[2]) begin`
327			int_vec <= #1 `OC8051_INT_X1;
328			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
329			`end else if (int_l0[3]) begin`
330			int_vec <= #1 `OC8051_INT_T1;
331			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
332			`end else if (int_l0[4]) begin`
333			int_vec <= #1 `OC8051_INT_UART;
334			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
335			`end else if (int_l0[5]) begin`
336			int_vec <= #1 `OC8051_INT_T2;
337			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
338			`end`
339			`end else begin`
340			`int_vec <= #1 8'h00;`
341			`end`
342			`end`
343
344
345			`always @(posedge clk or posedge rst)`
346			`if (rst) begin`
347			`tf0_buff <= #1 1'b0;`
348			`tf1_buff <= #1 1'b0;`
349			`ie0_buff <= #1 1'b0;`
350			`ie1_buff <= #1 1'b0;`
351			`end else begin`
352			`tf0_buff <= #1 tf0;`
353			`tf1_buff <= #1 tf1;`
354			`ie0_buff <= #1 ie0;`
355			`ie1_buff <= #1 ie1;`
356			`end`
357
358			`endmodule`