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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// 8051 program status word ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// Description ////
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//// program status word ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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// Revision 1.10 2003/04/07 14:58:02 simont
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// change sfr's interface.
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//
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// Revision 1.9 2003/01/13 14:14:41 simont
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// replace some modules
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//
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// Revision 1.8 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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//
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// Revision 1.7 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_psw (clk, rst, wr_addr, data_in, wr, wr_bit, data_out, p,
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cy_in, ac_in, ov_in, set, bank_sel);
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//
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// clk (in) clock
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// rst (in) reset
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// addr (in) write address [oc8051_ram_wr_sel.out]
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// data_in (in) data input [oc8051_alu.des1]
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// wr (in) write [oc8051_decoder.wr -r]
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// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
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// p (in) parity [oc8051_acc.p]
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// cy_in (in) input bit data [oc8051_alu.desCy]
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// ac_in (in) auxiliary carry input [oc8051_alu.desAc]
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// ov_in (in) overflov input [oc8051_alu.desOv]
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// set (in) set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
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//
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input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
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input [1:0] set;
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input [7:0] wr_addr, data_in;
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output [1:0] bank_sel;
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output [7:0] data_out;
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reg [7:1] data;
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wire wr_psw;
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assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
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assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
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assign data_out = {data[7:1], p};
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//
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//case writing to psw
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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data <= #1 `OC8051_RST_PSW;
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//
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// write to psw (byte addressable)
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else begin
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if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW))
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data[7:1] <= #1 data_in[7:1];
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//
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// write to psw (bit addressable)
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else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
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data[wr_addr[2:0]] <= #1 cy_in;
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else begin
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case (set) /* synopsys full_case parallel_case */
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`OC8051_PS_CY: begin
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//
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//write carry
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data[7] <= #1 cy_in;
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end
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`OC8051_PS_OV: begin
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//
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//write carry and overflov
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data[7] <= #1 cy_in;
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data[2] <= #1 ov_in;
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end
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`OC8051_PS_AC:begin
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//
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//write carry, overflov and ac
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data[7] <= #1 cy_in;
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data[6] <= #1 ac_in;
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data[2] <= #1 ov_in;
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end
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endcase
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end
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end
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end
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endmodule
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