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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 48

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores sfr top level module                             ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   special function registers for oc8051                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/05/07 12:39:20  simont
// fix bug in case of sequence of inc dptr instrucitons.
//
// Revision 1.13  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.12  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.11  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.10  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.9  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.8  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.5  2003/04/04 10:35:07  simont
// signal prsc_ow added.
//
// Revision 1.4  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.3  2003/01/21 13:51:30  simont
// add include oc8051_defines.v
//
// Revision 1.2  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.1  2002/11/05 17:22:27  simont
// initial import
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_sfr (rst, clk,
       adr0, adr1, dat0,
       dat1, dat2, bit_in,
       des_acc,
       we, wr_bit,
       bit_out,
       wr_sfr, acc,
       ram_wr_sel, ram_rd_sel,
       sp, sp_w,
       bank_sel,
       desAc, desOv,
       srcAc, cy,
       psw_set, rmw,
       comp_sel,
       comp_wait,
 
`ifdef OC8051_PORTS
 
  `ifdef OC8051_PORT0
       p0_out,
       p0_in,
  `endif
 
  `ifdef OC8051_PORT1
       p1_out,
       p1_in,
  `endif
 
  `ifdef OC8051_PORT2
       p2_out,
       p2_in,
  `endif
 
  `ifdef OC8051_PORT3
       p3_out,
       p3_in,
  `endif
 
`endif
 
 
  `ifdef OC8051_UART
       rxd, txd,
  `endif
 
       int_ack, intr,
       int0, int1,
       int_src,
       reti,
 
  `ifdef OC8051_TC01
       t0, t1,
  `endif
 
  `ifdef OC8051_TC2
       t2, t2ex,
  `endif
 
       dptr_hi, dptr_lo,
       wait_data);
 
 
input       rst,        // reset - pin
            clk,        // clock - pin
            we,         // write enable
            bit_in,
            desAc,
            desOv,
            rmw;
input       int_ack,
            int0,
            int1,
            reti,
            wr_bit;
input [1:0] psw_set,
            wr_sfr,
            comp_sel;
input [2:0] ram_rd_sel,
            ram_wr_sel;
input [7:0] adr0,        //address 0 input
            adr1,       //address 1 input
            des_acc,
            dat1,       //data 1 input (des1)
            dat2;       //data 2 input (des2)
 
output       bit_out,
             intr,
             srcAc,
             cy,
             wait_data,
             comp_wait;
output [1:0] bank_sel;
output [7:0] dat0,       //data output
             int_src,
             dptr_hi,
             dptr_lo,
             acc;
output [7:0] sp,
             sp_w;
 
// ports
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0] p0_in;
output [7:0] p0_out;
wire   [7:0] p0_data;
`endif
 
`ifdef OC8051_PORT1
input  [7:0] p1_in;
output [7:0] p1_out;
wire   [7:0] p1_data;
`endif
 
`ifdef OC8051_PORT2
input  [7:0] p2_in;
output [7:0] p2_out;
wire   [7:0] p2_data;
`endif
 
`ifdef OC8051_PORT3
input  [7:0] p3_in;
output [7:0] p3_out;
wire   [7:0] p3_data;
`endif
 
`endif
 
 
// serial interface
`ifdef OC8051_UART
input        rxd;
output       txd;
`endif
 
// timer/counter 0,1
`ifdef OC8051_TC01
input        t0, t1;
`endif
 
// timer/counter 2
`ifdef OC8051_TC2
input        t2, t2ex;
`endif
 
reg        bit_out,
           wait_data;
reg [7:0]  dat0,
           adr0_r;
 
reg        wr_bit_r;
reg [2:0]  ram_wr_sel_r;
 
 
wire       p,
           uart_int,
           tf0,
           tf1,
           tr0,
           tr1,
           rclk,
           tclk,
           brate2,
           tc2_int;
 
 
wire [7:0] b_reg,
           psw,
 
`ifdef OC8051_TC2
  // t/c 2
           t2con,
           tl2,
           th2,
           rcap2l,
           rcap2h,
`endif
 
`ifdef OC8051_TC01
  // t/c 0,1
           tmod,
           tl0,
           th0,
           tl1,
           th1,
`endif
 
  // serial interface
`ifdef OC8051_UART
           scon,
           pcon,
           sbuf,
`endif
 
  //interrupt control
           ie,
           tcon,
           ip;
 
 
reg        pres_ow;
reg [3:0]  prescaler;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
 
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk),
                       .rst(rst),
                       .bit_in(bit_in),
                       .data_in(des_acc),
                       .data2_in(dat2),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .wr_sfr(wr_sfr),
                       .wr_addr(adr1),
                       .data_out(acc),
                       .p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
                                     .rst(rst),
                                     .bit_in(bit_in),
                                     .data_in(des_acc),
                                     .wr(we),
                                     .wr_bit(wr_bit_r),
                                     .wr_addr(adr1),
                                     .data_out(b_reg));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk),
                     .rst(rst),
                     .ram_rd_sel(ram_rd_sel),
                     .ram_wr_sel(ram_wr_sel),
                     .wr_addr(adr1),
                     .wr(we),
                     .wr_bit(wr_bit_r),
                     .data_in(dat1),
                     .sp_out(sp),
                     .sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk),
                         .rst(rst),
                         .addr(adr1),
                         .data_in(des_acc),
                         .data2_in(dat2),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .data_hi(dptr_hi),
                         .data_lo(dptr_lo),
                         .wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk),
                        .rst(rst),
                        .wr_addr(adr1),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .data_out(psw),
                        .p(p),
                        .cy_in(bit_in),
                        .ac_in(desAc),
                        .ov_in(desOv),
                        .set(psw_set),
                        .bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
`ifdef OC8051_PORTS
  oc8051_ports oc8051_ports1(.clk(clk),
                           .rst(rst),
                           .bit_in(bit_in),
                           .data_in(dat1),
                           .wr(we),
                           .wr_bit(wr_bit_r),
                           .wr_addr(adr1),
 
                `ifdef OC8051_PORT0
                           .p0_out(p0_out),
                           .p0_in(p0_in),
                           .p0_data(p0_data),
                `endif
 
                `ifdef OC8051_PORT1
                           .p1_out(p1_out),
                           .p1_in(p1_in),
                           .p1_data(p1_data),
                `endif
 
                `ifdef OC8051_PORT2
                           .p2_out(p2_out),
                           .p2_in(p2_in),
                           .p2_data(p2_data),
                `endif
 
                `ifdef OC8051_PORT3
                           .p3_out(p3_out),
                           .p3_in(p3_in),
                           .p3_data(p3_data),
                `endif
 
                           .rmw(rmw));
`endif
 
//
// serial interface
// SCON, SBUF
`ifdef OC8051_UART
  oc8051_uart oc8051_uatr1 (.clk(clk),
                            .rst(rst),
                            .bit_in(bit_in),
                            .data_in(dat1),
                            .wr(we),
                            .wr_bit(wr_bit_r),
                            .wr_addr(adr1),
                            .rxd(rxd),
                            .txd(txd),
                // interrupt
                            .intr(uart_int),
                // baud rate sources
                            .brate2(brate2),
                            .t1_ow(tf1),
                            .pres_ow(pres_ow),
                            .rclk(rclk),
                            .tclk(tclk),
                //registers
                            .scon(scon),
                            .pcon(pcon),
                            .sbuf(sbuf));
`else
  assign uart_int = 1'b0;
`endif
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk),
                        .rst(rst),
                        .wr_addr(adr1),
                        .bit_in(bit_in),
                        .ack(int_ack),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .tf0(tf0),
                        .tf1(tf1),
                        .t2_int(tc2_int),
                        .tr0(tr0),
                        .tr1(tr1),
                        .ie0(int0),
                        .ie1(int1),
                        .uart_int(uart_int),
                        .reti(reti),
                        .intr(intr),
                        .int_vec(int_src),
                        .ie(ie),
                        .tcon(tcon),
                        .ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
`ifdef OC8051_TC01
  oc8051_tc oc8051_tc1(.clk(clk),
                       .rst(rst),
                       .wr_addr(adr1),
                       .data_in(dat1),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .ie0(int0),
                       .ie1(int1),
                       .tr0(tr0),
                       .tr1(tr1),
                       .t0(t0),
                       .t1(t1),
                       .tf0(tf0),
                       .tf1(tf1),
                       .pres_ow(pres_ow),
                       .tmod(tmod),
                       .tl0(tl0),
                       .th0(th0),
                       .tl1(tl1),
                       .th1(th1));
`else
  assign tf0 = 1'b0;
  assign tf1 = 1'b0;
`endif
 
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
`ifdef OC8051_TC2
  oc8051_tc2 oc8051_tc21(.clk(clk),
                         .rst(rst),
                         .wr_addr(adr1),
                         .data_in(dat1),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .bit_in(bit_in),
                         .t2(t2),
                         .t2ex(t2ex),
                         .rclk(rclk),
                         .tclk(tclk),
                         .brate2(brate2),
                         .tc2_int(tc2_int),
                         .pres_ow(pres_ow),
                         .t2con(t2con),
                         .tl2(tl2),
                         .th2(th2),
                         .rcap2l(rcap2l),
                         .rcap2h(rcap2h));
`else
  assign tc2_int = 1'b0;
  assign rclk    = 1'b0;
  assign tclk    = 1'b0;
  assign brate2  = 1'b0;
`endif
 
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    adr0_r <= #1 8'h00;
    ram_wr_sel_r <= #1 3'b000;
    wr_bit_r <= #1 1'b0;
//    wait_data <= #1 1'b0;
  end else begin
    adr0_r <= #1 adr0;
    ram_wr_sel_r <= #1 ram_wr_sel;
    wr_bit_r <= #1 wr_bit;
  end
 
assign comp_wait = !(
                    ((comp_sel==`OC8051_CSS_AZ) &
                       ((wr_sfr==`OC8051_WRS_ACC1) |
                        (wr_sfr==`OC8051_WRS_ACC2) |
                        ((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_CY) &
                       ((|psw_set) |
                        ((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_BIT) &
                       ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
                       ((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dat0 <= #1 8'h00;
    wait_data <= #1 1'b0;
  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address
    dat0 <= #1 des_acc;
    wait_data <= #1 1'b0;
  end else if (
      (
        ((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) |        //write to acc
//        ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) |  //write to dpl
        (adr1[7] & (adr1==adr0) & we & !wr_bit_r) |                     //write and read same address
        (adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) &  we & wr_bit_r) //write bit addressable to read address
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else if ((
      ((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
      ((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) |  //write to acc
      ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI))        //write to dph
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else begin
    case (adr0) /* synopsys full_case parallel_case */
      `OC8051_SFR_ACC:          dat0 <= #1 acc;
      `OC8051_SFR_PSW:          dat0 <= #1 psw;
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_P0:           dat0 <= #1 p0_data;
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_P1:           dat0 <= #1 p1_data;
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_P2:           dat0 <= #1 p2_data;
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_P3:           dat0 <= #1 p3_data;
  `endif
`endif
 
      `OC8051_SFR_SP:           dat0 <= #1 sp;
      `OC8051_SFR_B:            dat0 <= #1 b_reg;
      `OC8051_SFR_DPTR_HI:      dat0 <= #1 dptr_hi;
      `OC8051_SFR_DPTR_LO:      dat0 <= #1 dptr_lo;
 
`ifdef OC8051_UART
      `OC8051_SFR_SCON:         dat0 <= #1 scon;
      `OC8051_SFR_SBUF:         dat0 <= #1 sbuf;
      `OC8051_SFR_PCON:         dat0 <= #1 pcon;
`endif
 
`ifdef OC8051_TC01
      `OC8051_SFR_TH0:          dat0 <= #1 th0;
      `OC8051_SFR_TH1:          dat0 <= #1 th1;
      `OC8051_SFR_TL0:          dat0 <= #1 tl0;
      `OC8051_SFR_TL1:          dat0 <= #1 tl1;
      `OC8051_SFR_TMOD:         dat0 <= #1 tmod;
`endif
 
      `OC8051_SFR_IP:           dat0 <= #1 ip;
      `OC8051_SFR_IE:           dat0 <= #1 ie;
      `OC8051_SFR_TCON:         dat0 <= #1 tcon;
 
`ifdef OC8051_TC2
      `OC8051_SFR_RCAP2H:       dat0 <= #1 rcap2h;
      `OC8051_SFR_RCAP2L:       dat0 <= #1 rcap2l;
      `OC8051_SFR_TH2:          dat0 <= #1 th2;
      `OC8051_SFR_TL2:          dat0 <= #1 tl2;
      `OC8051_SFR_T2CON:        dat0 <= #1 t2con;
`endif
 
//      default:                        dat0 <= #1 8'h00;
    endcase
    wait_data <= #1 1'b0;
  end
end
 
 
//
//set output in case of address (bit)
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    bit_out <= #1 1'h0;
  else if (
          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC))         //write to acc
          )
 
    bit_out <= #1 dat1[adr0[2:0]];
  else if ((adr1==adr0) & we & wr_bit_r)
    bit_out <= #1 bit_in;
  else
    case (adr0[7:3]) /* synopsys full_case parallel_case */
      `OC8051_SFR_B_ACC:   bit_out <= #1 acc[adr0[2:0]];
      `OC8051_SFR_B_PSW:   bit_out <= #1 psw[adr0[2:0]];
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_B_P0:    bit_out <= #1 p0_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_B_P1:    bit_out <= #1 p1_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_B_P2:    bit_out <= #1 p2_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_B_P3:    bit_out <= #1 p3_data[adr0[2:0]];
  `endif
`endif
 
      `OC8051_SFR_B_B:     bit_out <= #1 b_reg[adr0[2:0]];
      `OC8051_SFR_B_IP:    bit_out <= #1 ip[adr0[2:0]];
      `OC8051_SFR_B_IE:    bit_out <= #1 ie[adr0[2:0]];
      `OC8051_SFR_B_TCON:  bit_out <= #1 tcon[adr0[2:0]];
 
`ifdef OC8051_UART
      `OC8051_SFR_B_SCON:  bit_out <= #1 scon[adr0[2:0]];
`endif
 
`ifdef OC8051_TC2
      `OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
`endif
 
//      default:             bit_out <= #1 1'b0;
    endcase
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b0;
  end else if (prescaler==4'b1011) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b1;
  end else begin
    prescaler <= #1 prescaler + 4'h1;
    pres_ow <= #1 1'b0;
  end
end
 
endmodule

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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores sfr top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// special function registers for oc8051 ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.14 2003/05/07 12:39:20 simont`
48			`// fix bug in case of sequence of inc dptr instrucitons.`
49			`//`
50			`// Revision 1.13 2003/05/05 15:46:37 simont`
51			`// add aditional alu destination to solve critical path.`
52			`//`
53			`// Revision 1.12 2003/04/29 11:24:31 simont`
54			`// fix bug in case execution of two data dependent instructions.`
55			`//`
56			`// Revision 1.11 2003/04/25 17:15:51 simont`
57			`// change branch instruction execution (reduse needed clock periods).`
58			`//`
59			`// Revision 1.10 2003/04/10 12:43:19 simont`
60			`// defines for pherypherals added`
61			`//`
62			`// Revision 1.9 2003/04/09 16:24:03 simont`
63			`// change wr_sft to 2 bit wire.`
64			`//`
65			`// Revision 1.8 2003/04/09 15:49:42 simont`
66			`// Register oc8051_sfr dato output, add signal wait_data.`
67			`//`
68			`// Revision 1.7 2003/04/07 14:58:02 simont`
69			`// change sfr's interface.`
70			`//`
71			`// Revision 1.6 2003/04/07 13:29:16 simont`
72			`// change uart to meet timing.`
73			`//`
74			`// Revision 1.5 2003/04/04 10:35:07 simont`
75			`// signal prsc_ow added.`
76			`//`
77			`// Revision 1.4 2003/03/28 17:45:57 simont`
78			`// change module name.`
79			`//`
80			`// Revision 1.3 2003/01/21 13:51:30 simont`
81			`// add include oc8051_defines.v`
82			`//`
83			`// Revision 1.2 2003/01/13 14:14:41 simont`
84			`// replace some modules`
85			`//`
86			`// Revision 1.1 2002/11/05 17:22:27 simont`
87			`// initial import`
88			`//`
89			`//`
90
91			`// synopsys translate_off`
92			`include "oc8051_timescale.v"
93			`// synopsys translate_on`
94
95			`include "oc8051_defines.v"
96
97
98			`module oc8051_sfr (rst, clk,`
99			`adr0, adr1, dat0,`
100			`dat1, dat2, bit_in,`
101			`des_acc,`
102			`we, wr_bit,`
103			`bit_out,`
104			`wr_sfr, acc,`
105			`ram_wr_sel, ram_rd_sel,`
106			`sp, sp_w,`
107			`bank_sel,`
108			`desAc, desOv,`
109			`srcAc, cy,`
110			`psw_set, rmw,`
111			`comp_sel,`
112			`comp_wait,`
113
114			`ifdef OC8051_PORTS
115
116			`ifdef OC8051_PORT0
117			`p0_out,`
118			`p0_in,`
119			`endif
120
121			`ifdef OC8051_PORT1
122			`p1_out,`
123			`p1_in,`
124			`endif
125
126			`ifdef OC8051_PORT2
127			`p2_out,`
128			`p2_in,`
129			`endif
130
131			`ifdef OC8051_PORT3
132			`p3_out,`
133			`p3_in,`
134			`endif
135
136			`endif
137
138
139			`ifdef OC8051_UART
140			`rxd, txd,`
141			`endif
142
143			`int_ack, intr,`
144			`int0, int1,`
145			`int_src,`
146			`reti,`
147
148			`ifdef OC8051_TC01
149			`t0, t1,`
150			`endif
151
152			`ifdef OC8051_TC2
153			`t2, t2ex,`
154			`endif
155
156			`dptr_hi, dptr_lo,`
157			`wait_data);`
158
159
160			`input rst, // reset - pin`
161			`clk, // clock - pin`
162			`we, // write enable`
163			`bit_in,`
164			`desAc,`
165			`desOv,`
166			`rmw;`
167			`input int_ack,`
168			`int0,`
169			`int1,`
170			`reti,`
171			`wr_bit;`
172			`input [1:0] psw_set,`
173			`wr_sfr,`
174			`comp_sel;`
175			`input [2:0] ram_rd_sel,`
176			`ram_wr_sel;`
177			`input [7:0] adr0, //address 0 input`
178			`adr1, //address 1 input`
179			`des_acc,`
180			`dat1, //data 1 input (des1)`
181			`dat2; //data 2 input (des2)`
182
183			`output bit_out,`
184			`intr,`
185			`srcAc,`
186			`cy,`
187			`wait_data,`
188			`comp_wait;`
189			`output [1:0] bank_sel;`
190			`output [7:0] dat0, //data output`
191			`int_src,`
192			`dptr_hi,`
193			`dptr_lo,`
194			`acc;`
195			`output [7:0] sp,`
196			`sp_w;`
197
198			`// ports`
199			`ifdef OC8051_PORTS
200
201			`ifdef OC8051_PORT0
202			`input [7:0] p0_in;`
203			`output [7:0] p0_out;`
204			`wire [7:0] p0_data;`
205			`endif
206
207			`ifdef OC8051_PORT1
208			`input [7:0] p1_in;`
209			`output [7:0] p1_out;`
210			`wire [7:0] p1_data;`
211			`endif
212
213			`ifdef OC8051_PORT2
214			`input [7:0] p2_in;`
215			`output [7:0] p2_out;`
216			`wire [7:0] p2_data;`
217			`endif
218
219			`ifdef OC8051_PORT3
220			`input [7:0] p3_in;`
221			`output [7:0] p3_out;`
222			`wire [7:0] p3_data;`
223			`endif
224
225			`endif
226
227
228			`// serial interface`
229			`ifdef OC8051_UART
230			`input rxd;`
231			`output txd;`
232			`endif
233
234			`// timer/counter 0,1`
235			`ifdef OC8051_TC01
236			`input t0, t1;`
237			`endif
238
239			`// timer/counter 2`
240			`ifdef OC8051_TC2
241			`input t2, t2ex;`
242			`endif
243
244			`reg bit_out,`
245			`wait_data;`
246			`reg [7:0] dat0,`
247			`adr0_r;`
248
249			`reg wr_bit_r;`
250			`reg [2:0] ram_wr_sel_r;`
251
252
253			`wire p,`
254			`uart_int,`
255			`tf0,`
256			`tf1,`
257			`tr0,`
258			`tr1,`
259			`rclk,`
260			`tclk,`
261			`brate2,`
262			`tc2_int;`
263
264
265			`wire [7:0] b_reg,`
266			`psw,`
267
268			`ifdef OC8051_TC2
269			`// t/c 2`
270			`t2con,`
271			`tl2,`
272			`th2,`
273			`rcap2l,`
274			`rcap2h,`
275			`endif
276
277			`ifdef OC8051_TC01
278			`// t/c 0,1`
279			`tmod,`
280			`tl0,`
281			`th0,`
282			`tl1,`
283			`th1,`
284			`endif
285
286			`// serial interface`
287			`ifdef OC8051_UART
288			`scon,`
289			`pcon,`
290			`sbuf,`
291			`endif
292
293			`//interrupt control`
294			`ie,`
295			`tcon,`
296			`ip;`
297
298
299			`reg pres_ow;`
300			`reg [3:0] prescaler;`
301
302
303			`assign cy = psw[7];`
304			`assign srcAc = psw [6];`
305
306
307
308			`//`
309			`// accumulator`
310			`// ACC`
311			`oc8051_acc oc8051_acc1(.clk(clk),`
312			`.rst(rst),`
313			`.bit_in(bit_in),`
314			`.data_in(des_acc),`
315			`.data2_in(dat2),`
316			`.wr(we),`
317			`.wr_bit(wr_bit_r),`
318			`.wr_sfr(wr_sfr),`
319			`.wr_addr(adr1),`
320			`.data_out(acc),`
321			`.p(p));`
322
323
324			`//`
325			`// b register`
326			`// B`
327			`oc8051_b_register oc8051_b_register (.clk(clk),`
328			`.rst(rst),`
329			`.bit_in(bit_in),`
330			`.data_in(des_acc),`
331			`.wr(we),`
332			`.wr_bit(wr_bit_r),`
333			`.wr_addr(adr1),`
334			`.data_out(b_reg));`
335
336			`//`
337			`//stack pointer`
338			`// SP`
339			`oc8051_sp oc8051_sp1(.clk(clk),`
340			`.rst(rst),`
341			`.ram_rd_sel(ram_rd_sel),`
342			`.ram_wr_sel(ram_wr_sel),`
343			`.wr_addr(adr1),`
344			`.wr(we),`
345			`.wr_bit(wr_bit_r),`
346			`.data_in(dat1),`
347			`.sp_out(sp),`
348			`.sp_w(sp_w));`
349
350			`//`
351			`//data pointer`
352			`// DPTR, DPH, DPL`
353			`oc8051_dptr oc8051_dptr1(.clk(clk),`
354			`.rst(rst),`
355			`.addr(adr1),`
356			`.data_in(des_acc),`
357			`.data2_in(dat2),`
358			`.wr(we),`
359			`.wr_bit(wr_bit_r),`
360			`.data_hi(dptr_hi),`
361			`.data_lo(dptr_lo),`
362			`.wr_sfr(wr_sfr));`
363
364
365			`//`
366			`//program status word`
367			`// PSW`
368			`oc8051_psw oc8051_psw1 (.clk(clk),`
369			`.rst(rst),`
370			`.wr_addr(adr1),`
371			`.data_in(dat1),`
372			`.wr(we),`
373			`.wr_bit(wr_bit_r),`
374			`.data_out(psw),`
375			`.p(p),`
376			`.cy_in(bit_in),`
377			`.ac_in(desAc),`
378			`.ov_in(desOv),`
379			`.set(psw_set),`
380			`.bank_sel(bank_sel));`
381
382			`//`
383			`// ports`
384			`// P0, P1, P2, P3`
385			`ifdef OC8051_PORTS
386			`oc8051_ports oc8051_ports1(.clk(clk),`
387			`.rst(rst),`
388			`.bit_in(bit_in),`
389			`.data_in(dat1),`
390			`.wr(we),`
391			`.wr_bit(wr_bit_r),`
392			`.wr_addr(adr1),`
393
394			`ifdef OC8051_PORT0
395			`.p0_out(p0_out),`
396			`.p0_in(p0_in),`
397			`.p0_data(p0_data),`
398			`endif
399
400			`ifdef OC8051_PORT1
401			`.p1_out(p1_out),`
402			`.p1_in(p1_in),`
403			`.p1_data(p1_data),`
404			`endif
405
406			`ifdef OC8051_PORT2
407			`.p2_out(p2_out),`
408			`.p2_in(p2_in),`
409			`.p2_data(p2_data),`
410			`endif
411
412			`ifdef OC8051_PORT3
413			`.p3_out(p3_out),`
414			`.p3_in(p3_in),`
415			`.p3_data(p3_data),`
416			`endif
417
418			`.rmw(rmw));`
419			`endif
420
421			`//`
422			`// serial interface`
423			`// SCON, SBUF`
424			`ifdef OC8051_UART
425			`oc8051_uart oc8051_uatr1 (.clk(clk),`
426			`.rst(rst),`
427			`.bit_in(bit_in),`
428			`.data_in(dat1),`
429			`.wr(we),`
430			`.wr_bit(wr_bit_r),`
431			`.wr_addr(adr1),`
432			`.rxd(rxd),`
433			`.txd(txd),`
434			`// interrupt`
435			`.intr(uart_int),`
436			`// baud rate sources`
437			`.brate2(brate2),`
438			`.t1_ow(tf1),`
439			`.pres_ow(pres_ow),`
440			`.rclk(rclk),`
441			`.tclk(tclk),`
442			`//registers`
443			`.scon(scon),`
444			`.pcon(pcon),`
445			`.sbuf(sbuf));`
446			`else
447			`assign uart_int = 1'b0;`
448			`endif
449
450			`//`
451			`// interrupt control`
452			`// IP, IE, TCON`
453			`oc8051_int oc8051_int1 (.clk(clk),`
454			`.rst(rst),`
455			`.wr_addr(adr1),`
456			`.bit_in(bit_in),`
457			`.ack(int_ack),`
458			`.data_in(dat1),`
459			`.wr(we),`
460			`.wr_bit(wr_bit_r),`
461			`.tf0(tf0),`
462			`.tf1(tf1),`
463			`.t2_int(tc2_int),`
464			`.tr0(tr0),`
465			`.tr1(tr1),`
466			`.ie0(int0),`
467			`.ie1(int1),`
468			`.uart_int(uart_int),`
469			`.reti(reti),`
470			`.intr(intr),`
471			`.int_vec(int_src),`
472			`.ie(ie),`
473			`.tcon(tcon),`
474			`.ip(ip));`
475
476
477			`//`
478			`// timer/counter control`
479			`// TH0, TH1, TL0, TH1, TMOD`
480			`ifdef OC8051_TC01
481			`oc8051_tc oc8051_tc1(.clk(clk),`
482			`.rst(rst),`
483			`.wr_addr(adr1),`
484			`.data_in(dat1),`
485			`.wr(we),`
486			`.wr_bit(wr_bit_r),`
487			`.ie0(int0),`
488			`.ie1(int1),`
489			`.tr0(tr0),`
490			`.tr1(tr1),`
491			`.t0(t0),`
492			`.t1(t1),`
493			`.tf0(tf0),`
494			`.tf1(tf1),`
495			`.pres_ow(pres_ow),`
496			`.tmod(tmod),`
497			`.tl0(tl0),`
498			`.th0(th0),`
499			`.tl1(tl1),`
500			`.th1(th1));`
501			`else
502			`assign tf0 = 1'b0;`
503			`assign tf1 = 1'b0;`
504			`endif
505
506			`//`
507			`// timer/counter 2`
508			`// TH2, TL2, RCAPL2L, RCAPL2H, T2CON`
509			`ifdef OC8051_TC2
510			`oc8051_tc2 oc8051_tc21(.clk(clk),`
511			`.rst(rst),`
512			`.wr_addr(adr1),`
513			`.data_in(dat1),`
514			`.wr(we),`
515			`.wr_bit(wr_bit_r),`
516			`.bit_in(bit_in),`
517			`.t2(t2),`
518			`.t2ex(t2ex),`
519			`.rclk(rclk),`
520			`.tclk(tclk),`
521			`.brate2(brate2),`
522			`.tc2_int(tc2_int),`
523			`.pres_ow(pres_ow),`
524			`.t2con(t2con),`
525			`.tl2(tl2),`
526			`.th2(th2),`
527			`.rcap2l(rcap2l),`
528			`.rcap2h(rcap2h));`
529			`else
530			`assign tc2_int = 1'b0;`
531			`assign rclk = 1'b0;`
532			`assign tclk = 1'b0;`
533			`assign brate2 = 1'b0;`
534			`endif
535
536
537
538			`always @(posedge clk or posedge rst)`
539			`if (rst) begin`
540			`adr0_r <= #1 8'h00;`
541			`ram_wr_sel_r <= #1 3'b000;`
542			`wr_bit_r <= #1 1'b0;`
543			`// wait_data <= #1 1'b0;`
544			`end else begin`
545			`adr0_r <= #1 adr0;`
546			`ram_wr_sel_r <= #1 ram_wr_sel;`
547			`wr_bit_r <= #1 wr_bit;`
548			`end`
549
550			`assign comp_wait = !(`
551			((comp_sel==`OC8051_CSS_AZ) &
552			((wr_sfr==`OC8051_WRS_ACC1) \|
553			(wr_sfr==`OC8051_WRS_ACC2) \|
554			((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) \|
555			((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) \|
556			((comp_sel==`OC8051_CSS_CY) &
557			`((\|psw_set) \|`
558			((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) \|
559			((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) \|
560			((comp_sel==`OC8051_CSS_BIT) &
561			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
562			`((adr1==adr0) & adr1[7] & we & !wr_bit_r)));`
563
564
565
566			`//`
567			`//set output in case of address (byte)`
568			`always @(posedge clk or posedge rst)`
569			`begin`
570			`if (rst) begin`
571			`dat0 <= #1 8'h00;`
572			`wait_data <= #1 1'b0;`
573			end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
574			`dat0 <= #1 des_acc;`
575			`wait_data <= #1 1'b0;`
576			`end else if (`
577			`(`
578			((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
579			// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) \| //write to dpl
580			`(adr1[7] & (adr1==adr0) & we & !wr_bit_r) \| //write and read same address`
581			`(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address`
582			`) & !wait_data) begin`
583			`wait_data <= #1 1'b1;`
584
585			`end else if ((`
586			((\|psw_set) & (adr0==`OC8051_SFR_PSW)) \|
587			((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
588			((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
589			`) & !wait_data) begin`
590			`wait_data <= #1 1'b1;`
591
592			`end else begin`
593			`case (adr0) /* synopsys full_case parallel_case */`
594			`OC8051_SFR_ACC: dat0 <= #1 acc;
595			`OC8051_SFR_PSW: dat0 <= #1 psw;
596
597			`ifdef OC8051_PORTS
598			`ifdef OC8051_PORT0
599			`OC8051_SFR_P0: dat0 <= #1 p0_data;
600			`endif
601
602			`ifdef OC8051_PORT1
603			`OC8051_SFR_P1: dat0 <= #1 p1_data;
604			`endif
605
606			`ifdef OC8051_PORT2
607			`OC8051_SFR_P2: dat0 <= #1 p2_data;
608			`endif
609
610			`ifdef OC8051_PORT3
611			`OC8051_SFR_P3: dat0 <= #1 p3_data;
612			`endif
613			`endif
614
615			`OC8051_SFR_SP: dat0 <= #1 sp;
616			`OC8051_SFR_B: dat0 <= #1 b_reg;
617			`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
618			`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
619
620			`ifdef OC8051_UART
621			`OC8051_SFR_SCON: dat0 <= #1 scon;
622			`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
623			`OC8051_SFR_PCON: dat0 <= #1 pcon;
624			`endif
625
626			`ifdef OC8051_TC01
627			`OC8051_SFR_TH0: dat0 <= #1 th0;
628			`OC8051_SFR_TH1: dat0 <= #1 th1;
629			`OC8051_SFR_TL0: dat0 <= #1 tl0;
630			`OC8051_SFR_TL1: dat0 <= #1 tl1;
631			`OC8051_SFR_TMOD: dat0 <= #1 tmod;
632			`endif
633
634			`OC8051_SFR_IP: dat0 <= #1 ip;
635			`OC8051_SFR_IE: dat0 <= #1 ie;
636			`OC8051_SFR_TCON: dat0 <= #1 tcon;
637
638			`ifdef OC8051_TC2
639			`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
640			`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
641			`OC8051_SFR_TH2: dat0 <= #1 th2;
642			`OC8051_SFR_TL2: dat0 <= #1 tl2;
643			`OC8051_SFR_T2CON: dat0 <= #1 t2con;
644			`endif
645
646			`// default: dat0 <= #1 8'h00;`
647			`endcase`
648			`wait_data <= #1 1'b0;`
649			`end`
650			`end`
651
652
653			`//`
654			`//set output in case of address (bit)`
655
656			`always @(posedge clk or posedge rst)`
657			`begin`
658			`if (rst)`
659			`bit_out <= #1 1'h0;`
660			`else if (`
661			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
662			((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
663			`)`
664
665			`bit_out <= #1 dat1[adr0[2:0]];`
666			`else if ((adr1==adr0) & we & wr_bit_r)`
667			`bit_out <= #1 bit_in;`
668			`else`
669			`case (adr0[7:3]) /* synopsys full_case parallel_case */`
670			`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
671			`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
672
673			`ifdef OC8051_PORTS
674			`ifdef OC8051_PORT0
675			`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
676			`endif
677
678			`ifdef OC8051_PORT1
679			`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
680			`endif
681
682			`ifdef OC8051_PORT2
683			`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
684			`endif
685
686			`ifdef OC8051_PORT3
687			`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
688			`endif
689			`endif
690
691			`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
692			`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
693			`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
694			`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
695
696			`ifdef OC8051_UART
697			`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
698			`endif
699
700			`ifdef OC8051_TC2
701			`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
702			`endif
703
704			`// default: bit_out <= #1 1'b0;`
705			`endcase`
706			`end`
707
708			`always @(posedge clk or posedge rst)`
709			`begin`
710			`if (rst) begin`
711			`prescaler <= #1 4'h0;`
712			`pres_ow <= #1 1'b0;`
713			`end else if (prescaler==4'b1011) begin`
714			`prescaler <= #1 4'h0;`
715			`pres_ow <= #1 1'b1;`
716			`end else begin`
717			`prescaler <= #1 prescaler + 4'h1;`
718			`pres_ow <= #1 1'b0;`
719			`end`
720			`end`
721
722			`endmodule`