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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 78

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores sfr top level module                             ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////   special function registers for oc8051                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/05/07 12:39:20  simont
// fix bug in case of sequence of inc dptr instrucitons.
//
// Revision 1.13  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.12  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.11  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.10  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.9  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.8  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.5  2003/04/04 10:35:07  simont
// signal prsc_ow added.
//
// Revision 1.4  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.3  2003/01/21 13:51:30  simont
// add include oc8051_defines.v
//
// Revision 1.2  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.1  2002/11/05 17:22:27  simont
// initial import
//
//
 
 
`include "top_defines.v"
 
 
module oc8051_sfr (rst, clk,
       adr0, adr1, dat0,
       dat1, dat2, bit_in,
       des_acc,
       we, wr_bit,
       bit_out,
       wr_sfr, acc,
       ram_wr_sel, ram_rd_sel,
       sp, sp_w,
       bank_sel,
       desAc, desOv,
       srcAc, cy,
       psw_set, rmw,
       comp_sel,
       comp_wait,
 
`ifdef OC8051_PORTS
 
  `ifdef OC8051_PORT0
       p0_out,
       p0_in,
  `endif
 
  `ifdef OC8051_PORT1
       p1_out,
       p1_in,
  `endif
 
  `ifdef OC8051_PORT2
       p2_out,
       p2_in,
  `endif
 
  `ifdef OC8051_PORT3
       p3_out,
       p3_in,
  `endif
 
`endif
 
 
  `ifdef OC8051_UART
       rxd, txd,
  `endif
 
       int_ack, intr,
       int0, int1,
       int_src,
       reti,
 
  `ifdef OC8051_TC01
       t0, t1,
  `endif
 
  `ifdef OC8051_TC2
       t2, t2ex,
  `endif
 
       dptr_hi, dptr_lo,
       wait_data);
 
 
input       rst,        // reset - pin
            clk,        // clock - pin
            we,         // write enable
            bit_in,
            desAc,
            desOv,
            rmw;
input       int_ack,
            int0,
            int1,
            reti,
            wr_bit;
input [1:0] psw_set,
            wr_sfr,
            comp_sel;
input [2:0] ram_rd_sel,
            ram_wr_sel;
input [7:0] adr0,        //address 0 input
            adr1,       //address 1 input
            des_acc,
            dat1,       //data 1 input (des1)
            dat2;       //data 2 input (des2)
 
output       bit_out,
             intr,
             srcAc,
             cy,
             wait_data,
             comp_wait;
output [1:0] bank_sel;
output [7:0] dat0,       //data output
             int_src,
             dptr_hi,
             dptr_lo,
             acc;
output [7:0] sp,
             sp_w;
 
// ports
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0] p0_in;
output [7:0] p0_out;
wire   [7:0] p0_data;
`endif
 
`ifdef OC8051_PORT1
input  [7:0] p1_in;
output [7:0] p1_out;
wire   [7:0] p1_data;
`endif
 
`ifdef OC8051_PORT2
input  [7:0] p2_in;
output [7:0] p2_out;
wire   [7:0] p2_data;
`endif
 
`ifdef OC8051_PORT3
input  [7:0] p3_in;
output [7:0] p3_out;
wire   [7:0] p3_data;
`endif
 
`endif
 
 
// serial interface
`ifdef OC8051_UART
input        rxd;
output       txd;
`endif
 
// timer/counter 0,1
`ifdef OC8051_TC01
input        t0, t1;
`endif
 
// timer/counter 2
`ifdef OC8051_TC2
input        t2, t2ex;
`endif
 
reg        bit_out,
           wait_data;
reg [7:0]  dat0,
           adr0_r;
 
reg        wr_bit_r;
reg [2:0]  ram_wr_sel_r;
 
 
wire       p,
           uart_int,
           tf0,
           tf1,
           tr0,
           tr1,
           rclk,
           tclk,
           brate2,
           tc2_int;
 
 
wire [7:0] b_reg,
           psw,
 
`ifdef OC8051_TC2
  // t/c 2
           t2con,
           tl2,
           th2,
           rcap2l,
           rcap2h,
`endif
 
`ifdef OC8051_TC01
  // t/c 0,1
           tmod,
           tl0,
           th0,
           tl1,
           th1,
`endif
 
  // serial interface
`ifdef OC8051_UART
           scon,
           pcon,
           sbuf,
`endif
 
  //interrupt control
           ie,
           tcon,
           ip;
 
 
reg        pres_ow;
reg [3:0]  prescaler;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
 
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk),
                       .rst(rst),
                       .bit_in(bit_in),
                       .data_in(des_acc),
                       .data2_in(dat2),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .wr_sfr(wr_sfr),
                       .wr_addr(adr1),
                       .data_out(acc),
                       .p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
                                     .rst(rst),
                                     .bit_in(bit_in),
                                     .data_in(des_acc),
                                     .wr(we),
                                     .wr_bit(wr_bit_r),
                                     .wr_addr(adr1),
                                     .data_out(b_reg));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk),
                     .rst(rst),
                     .ram_rd_sel(ram_rd_sel),
                     .ram_wr_sel(ram_wr_sel),
                     .wr_addr(adr1),
                     .wr(we),
                     .wr_bit(wr_bit_r),
                     .data_in(dat1),
                     .sp_out(sp),
                     .sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk),
                         .rst(rst),
                         .addr(adr1),
                         .data_in(des_acc),
                         .data2_in(dat2),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .data_hi(dptr_hi),
                         .data_lo(dptr_lo),
                         .wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk),
                        .rst(rst),
                        .wr_addr(adr1),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .data_out(psw),
                        .p(p),
                        .cy_in(bit_in),
                        .ac_in(desAc),
                        .ov_in(desOv),
                        .set(psw_set),
                        .bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
`ifdef OC8051_PORTS
  oc8051_ports oc8051_ports1(.clk(clk),
                           .rst(rst),
                           .bit_in(bit_in),
                           .data_in(dat1),
                           .wr(we),
                           .wr_bit(wr_bit_r),
                           .wr_addr(adr1),
 
                `ifdef OC8051_PORT0
                           .p0_out(p0_out),
                           .p0_in(p0_in),
                           .p0_data(p0_data),
                `endif
 
                `ifdef OC8051_PORT1
                           .p1_out(p1_out),
                           .p1_in(p1_in),
                           .p1_data(p1_data),
                `endif
 
                `ifdef OC8051_PORT2
                           .p2_out(p2_out),
                           .p2_in(p2_in),
                           .p2_data(p2_data),
                `endif
 
                `ifdef OC8051_PORT3
                           .p3_out(p3_out),
                           .p3_in(p3_in),
                           .p3_data(p3_data),
                `endif
 
                           .rmw(rmw));
`endif
 
//
// serial interface
// SCON, SBUF
`ifdef OC8051_UART
  oc8051_uart oc8051_uatr1 (.clk(clk),
                            .rst(rst),
                            .bit_in(bit_in),
                            .data_in(dat1),
                            .wr(we),
                            .wr_bit(wr_bit_r),
                            .wr_addr(adr1),
                            .rxd(rxd),
                            .txd(txd),
                // interrupt
                            .intr(uart_int),
                // baud rate sources
                            .brate2(brate2),
                            .t1_ow(tf1),
                            .pres_ow(pres_ow),
                            .rclk(rclk),
                            .tclk(tclk),
                //registers
                            .scon(scon),
                            .pcon(pcon),
                            .sbuf(sbuf));
`else
  assign uart_int = 1'b0;
`endif
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk),
                        .rst(rst),
                        .wr_addr(adr1),
                        .bit_in(bit_in),
                        .ack(int_ack),
                        .data_in(dat1),
                        .wr(we),
                        .wr_bit(wr_bit_r),
                        .tf0(tf0),
                        .tf1(tf1),
                        .t2_int(tc2_int),
                        .tr0(tr0),
                        .tr1(tr1),
                        .ie0(int0),
                        .ie1(int1),
                        .uart_int(uart_int),
                        .reti(reti),
                        .intr(intr),
                        .int_vec(int_src),
                        .ie(ie),
                        .tcon(tcon),
                        .ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
`ifdef OC8051_TC01
  oc8051_tc oc8051_tc1(.clk(clk),
                       .rst(rst),
                       .wr_addr(adr1),
                       .data_in(dat1),
                       .wr(we),
                       .wr_bit(wr_bit_r),
                       .ie0(int0),
                       .ie1(int1),
                       .tr0(tr0),
                       .tr1(tr1),
                       .t0(t0),
                       .t1(t1),
                       .tf0(tf0),
                       .tf1(tf1),
                       .pres_ow(pres_ow),
                       .tmod(tmod),
                       .tl0(tl0),
                       .th0(th0),
                       .tl1(tl1),
                       .th1(th1));
`else
  assign tf0 = 1'b0;
  assign tf1 = 1'b0;
`endif
 
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
`ifdef OC8051_TC2
  oc8051_tc2 oc8051_tc21(.clk(clk),
                         .rst(rst),
                         .wr_addr(adr1),
                         .data_in(dat1),
                         .wr(we),
                         .wr_bit(wr_bit_r),
                         .bit_in(bit_in),
                         .t2(t2),
                         .t2ex(t2ex),
                         .rclk(rclk),
                         .tclk(tclk),
                         .brate2(brate2),
                         .tc2_int(tc2_int),
                         .pres_ow(pres_ow),
                         .t2con(t2con),
                         .tl2(tl2),
                         .th2(th2),
                         .rcap2l(rcap2l),
                         .rcap2h(rcap2h));
`else
  assign tc2_int = 1'b0;
  assign rclk    = 1'b0;
  assign tclk    = 1'b0;
  assign brate2  = 1'b0;
`endif
 
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    adr0_r <= #1 8'h00;
    ram_wr_sel_r <= #1 3'b000;
    wr_bit_r <= #1 1'b0;
//    wait_data <= #1 1'b0;
  end else begin
    adr0_r <= #1 adr0;
    ram_wr_sel_r <= #1 ram_wr_sel;
    wr_bit_r <= #1 wr_bit;
  end
 
assign comp_wait = !(
                    ((comp_sel==`OC8051_CSS_AZ) &
                       ((wr_sfr==`OC8051_WRS_ACC1) |
                        (wr_sfr==`OC8051_WRS_ACC2) |
                        ((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_CY) &
                       ((|psw_set) |
                        ((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
                        ((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
                    ((comp_sel==`OC8051_CSS_BIT) &
                       ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
                       ((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dat0 <= #1 8'h00;
    wait_data <= #1 1'b0;
  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address
    dat0 <= #1 des_acc;
    wait_data <= #1 1'b0;
  end else if (
      (
        ((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) |        //write to acc
//        ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) |  //write to dpl
        (adr1[7] & (adr1==adr0) & we & !wr_bit_r) |                     //write and read same address
        (adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) &  we & wr_bit_r) //write bit addressable to read address
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else if ((
      ((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
      ((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) |  //write to acc
      ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI))        //write to dph
      ) & !wait_data) begin
    wait_data <= #1 1'b1;
 
  end else begin
    case (adr0) /* synopsys full_case parallel_case */
      `OC8051_SFR_ACC:          dat0 <= #1 acc;
      `OC8051_SFR_PSW:          dat0 <= #1 psw;
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_P0:           dat0 <= #1 p0_data;
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_P1:           dat0 <= #1 p1_data;
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_P2:           dat0 <= #1 p2_data;
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_P3:           dat0 <= #1 p3_data;
  `endif
`endif
 
      `OC8051_SFR_SP:           dat0 <= #1 sp;
      `OC8051_SFR_B:            dat0 <= #1 b_reg;
      `OC8051_SFR_DPTR_HI:      dat0 <= #1 dptr_hi;
      `OC8051_SFR_DPTR_LO:      dat0 <= #1 dptr_lo;
 
`ifdef OC8051_UART
      `OC8051_SFR_SCON:         dat0 <= #1 scon;
      `OC8051_SFR_SBUF:         dat0 <= #1 sbuf;
      `OC8051_SFR_PCON:         dat0 <= #1 pcon;
`endif
 
`ifdef OC8051_TC01
      `OC8051_SFR_TH0:          dat0 <= #1 th0;
      `OC8051_SFR_TH1:          dat0 <= #1 th1;
      `OC8051_SFR_TL0:          dat0 <= #1 tl0;
      `OC8051_SFR_TL1:          dat0 <= #1 tl1;
      `OC8051_SFR_TMOD:         dat0 <= #1 tmod;
`endif
 
      `OC8051_SFR_IP:           dat0 <= #1 ip;
      `OC8051_SFR_IE:           dat0 <= #1 ie;
      `OC8051_SFR_TCON:         dat0 <= #1 tcon;
 
`ifdef OC8051_TC2
      `OC8051_SFR_RCAP2H:       dat0 <= #1 rcap2h;
      `OC8051_SFR_RCAP2L:       dat0 <= #1 rcap2l;
      `OC8051_SFR_TH2:          dat0 <= #1 th2;
      `OC8051_SFR_TL2:          dat0 <= #1 tl2;
      `OC8051_SFR_T2CON:        dat0 <= #1 t2con;
`endif
 
//      default:                        dat0 <= #1 8'h00;
    endcase
    wait_data <= #1 1'b0;
  end
end
 
 
//
//set output in case of address (bit)
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    bit_out <= #1 1'h0;
  else if (
          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC))         //write to acc
          )
 
    bit_out <= #1 dat1[adr0[2:0]];
  else if ((adr1==adr0) & we & wr_bit_r)
    bit_out <= #1 bit_in;
  else
    case (adr0[7:3]) /* synopsys full_case parallel_case */
      `OC8051_SFR_B_ACC:   bit_out <= #1 acc[adr0[2:0]];
      `OC8051_SFR_B_PSW:   bit_out <= #1 psw[adr0[2:0]];
 
`ifdef OC8051_PORTS
  `ifdef OC8051_PORT0
      `OC8051_SFR_B_P0:    bit_out <= #1 p0_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT1
      `OC8051_SFR_B_P1:    bit_out <= #1 p1_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT2
      `OC8051_SFR_B_P2:    bit_out <= #1 p2_data[adr0[2:0]];
  `endif
 
  `ifdef OC8051_PORT3
      `OC8051_SFR_B_P3:    bit_out <= #1 p3_data[adr0[2:0]];
  `endif
`endif
 
      `OC8051_SFR_B_B:     bit_out <= #1 b_reg[adr0[2:0]];
      `OC8051_SFR_B_IP:    bit_out <= #1 ip[adr0[2:0]];
      `OC8051_SFR_B_IE:    bit_out <= #1 ie[adr0[2:0]];
      `OC8051_SFR_B_TCON:  bit_out <= #1 tcon[adr0[2:0]];
 
`ifdef OC8051_UART
      `OC8051_SFR_B_SCON:  bit_out <= #1 scon[adr0[2:0]];
`endif
 
`ifdef OC8051_TC2
      `OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
`endif
 
//      default:             bit_out <= #1 1'b0;
    endcase
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b0;
  end else if (prescaler==4'b1011) begin
    prescaler <= #1 4'h0;
    pres_ow <= #1 1'b1;
  end else begin
    prescaler <= #1 prescaler + 4'h1;
    pres_ow <= #1 1'b0;
  end
end
 
endmodule

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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_sfr.v] - Blame information for rev 78

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores sfr top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6	76	dinesha	`//// http://www.opencores.org/cores/turbo8051/ ////`
7	2	dinesha	`//// ////`
8			`//// Description ////`
9			`//// special function registers for oc8051 ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16	76	dinesha	`//// - Dinesh Annayya, dinesha@opencores.org ////`
17	2	dinesha	`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.14 2003/05/07 12:39:20 simont`
49			`// fix bug in case of sequence of inc dptr instrucitons.`
50			`//`
51			`// Revision 1.13 2003/05/05 15:46:37 simont`
52			`// add aditional alu destination to solve critical path.`
53			`//`
54			`// Revision 1.12 2003/04/29 11:24:31 simont`
55			`// fix bug in case execution of two data dependent instructions.`
56			`//`
57			`// Revision 1.11 2003/04/25 17:15:51 simont`
58			`// change branch instruction execution (reduse needed clock periods).`
59			`//`
60			`// Revision 1.10 2003/04/10 12:43:19 simont`
61			`// defines for pherypherals added`
62			`//`
63			`// Revision 1.9 2003/04/09 16:24:03 simont`
64			`// change wr_sft to 2 bit wire.`
65			`//`
66			`// Revision 1.8 2003/04/09 15:49:42 simont`
67			`// Register oc8051_sfr dato output, add signal wait_data.`
68			`//`
69			`// Revision 1.7 2003/04/07 14:58:02 simont`
70			`// change sfr's interface.`
71			`//`
72			`// Revision 1.6 2003/04/07 13:29:16 simont`
73			`// change uart to meet timing.`
74			`//`
75			`// Revision 1.5 2003/04/04 10:35:07 simont`
76			`// signal prsc_ow added.`
77			`//`
78			`// Revision 1.4 2003/03/28 17:45:57 simont`
79			`// change module name.`
80			`//`
81			`// Revision 1.3 2003/01/21 13:51:30 simont`
82			`// add include oc8051_defines.v`
83			`//`
84			`// Revision 1.2 2003/01/13 14:14:41 simont`
85			`// replace some modules`
86			`//`
87			`// Revision 1.1 2002/11/05 17:22:27 simont`
88			`// initial import`
89			`//`
90			`//`
91
92
93	76	dinesha	`include "top_defines.v"
94	2	dinesha
95
96			`module oc8051_sfr (rst, clk,`
97			`adr0, adr1, dat0,`
98			`dat1, dat2, bit_in,`
99			`des_acc,`
100			`we, wr_bit,`
101			`bit_out,`
102			`wr_sfr, acc,`
103			`ram_wr_sel, ram_rd_sel,`
104			`sp, sp_w,`
105			`bank_sel,`
106			`desAc, desOv,`
107			`srcAc, cy,`
108			`psw_set, rmw,`
109			`comp_sel,`
110			`comp_wait,`
111
112			`ifdef OC8051_PORTS
113
114			`ifdef OC8051_PORT0
115			`p0_out,`
116			`p0_in,`
117			`endif
118
119			`ifdef OC8051_PORT1
120			`p1_out,`
121			`p1_in,`
122			`endif
123
124			`ifdef OC8051_PORT2
125			`p2_out,`
126			`p2_in,`
127			`endif
128
129			`ifdef OC8051_PORT3
130			`p3_out,`
131			`p3_in,`
132			`endif
133
134			`endif
135
136
137			`ifdef OC8051_UART
138			`rxd, txd,`
139			`endif
140
141			`int_ack, intr,`
142			`int0, int1,`
143			`int_src,`
144			`reti,`
145
146			`ifdef OC8051_TC01
147			`t0, t1,`
148			`endif
149
150			`ifdef OC8051_TC2
151			`t2, t2ex,`
152			`endif
153
154			`dptr_hi, dptr_lo,`
155			`wait_data);`
156
157
158			`input rst, // reset - pin`
159			`clk, // clock - pin`
160			`we, // write enable`
161			`bit_in,`
162			`desAc,`
163			`desOv,`
164			`rmw;`
165			`input int_ack,`
166			`int0,`
167			`int1,`
168			`reti,`
169			`wr_bit;`
170			`input [1:0] psw_set,`
171			`wr_sfr,`
172			`comp_sel;`
173			`input [2:0] ram_rd_sel,`
174			`ram_wr_sel;`
175			`input [7:0] adr0, //address 0 input`
176			`adr1, //address 1 input`
177			`des_acc,`
178			`dat1, //data 1 input (des1)`
179			`dat2; //data 2 input (des2)`
180
181			`output bit_out,`
182			`intr,`
183			`srcAc,`
184			`cy,`
185			`wait_data,`
186			`comp_wait;`
187			`output [1:0] bank_sel;`
188			`output [7:0] dat0, //data output`
189			`int_src,`
190			`dptr_hi,`
191			`dptr_lo,`
192			`acc;`
193			`output [7:0] sp,`
194			`sp_w;`
195
196			`// ports`
197			`ifdef OC8051_PORTS
198
199			`ifdef OC8051_PORT0
200			`input [7:0] p0_in;`
201			`output [7:0] p0_out;`
202			`wire [7:0] p0_data;`
203			`endif
204
205			`ifdef OC8051_PORT1
206			`input [7:0] p1_in;`
207			`output [7:0] p1_out;`
208			`wire [7:0] p1_data;`
209			`endif
210
211			`ifdef OC8051_PORT2
212			`input [7:0] p2_in;`
213			`output [7:0] p2_out;`
214			`wire [7:0] p2_data;`
215			`endif
216
217			`ifdef OC8051_PORT3
218			`input [7:0] p3_in;`
219			`output [7:0] p3_out;`
220			`wire [7:0] p3_data;`
221			`endif
222
223			`endif
224
225
226			`// serial interface`
227			`ifdef OC8051_UART
228			`input rxd;`
229			`output txd;`
230			`endif
231
232			`// timer/counter 0,1`
233			`ifdef OC8051_TC01
234			`input t0, t1;`
235			`endif
236
237			`// timer/counter 2`
238			`ifdef OC8051_TC2
239			`input t2, t2ex;`
240			`endif
241
242			`reg bit_out,`
243			`wait_data;`
244			`reg [7:0] dat0,`
245			`adr0_r;`
246
247			`reg wr_bit_r;`
248			`reg [2:0] ram_wr_sel_r;`
249
250
251			`wire p,`
252			`uart_int,`
253			`tf0,`
254			`tf1,`
255			`tr0,`
256			`tr1,`
257			`rclk,`
258			`tclk,`
259			`brate2,`
260			`tc2_int;`
261
262
263			`wire [7:0] b_reg,`
264			`psw,`
265
266			`ifdef OC8051_TC2
267			`// t/c 2`
268			`t2con,`
269			`tl2,`
270			`th2,`
271			`rcap2l,`
272			`rcap2h,`
273			`endif
274
275			`ifdef OC8051_TC01
276			`// t/c 0,1`
277			`tmod,`
278			`tl0,`
279			`th0,`
280			`tl1,`
281			`th1,`
282			`endif
283
284			`// serial interface`
285			`ifdef OC8051_UART
286			`scon,`
287			`pcon,`
288			`sbuf,`
289			`endif
290
291			`//interrupt control`
292			`ie,`
293			`tcon,`
294			`ip;`
295
296
297			`reg pres_ow;`
298			`reg [3:0] prescaler;`
299
300
301			`assign cy = psw[7];`
302			`assign srcAc = psw [6];`
303
304
305
306			`//`
307			`// accumulator`
308			`// ACC`
309			`oc8051_acc oc8051_acc1(.clk(clk),`
310			`.rst(rst),`
311			`.bit_in(bit_in),`
312			`.data_in(des_acc),`
313			`.data2_in(dat2),`
314			`.wr(we),`
315			`.wr_bit(wr_bit_r),`
316			`.wr_sfr(wr_sfr),`
317			`.wr_addr(adr1),`
318			`.data_out(acc),`
319			`.p(p));`
320
321
322			`//`
323			`// b register`
324			`// B`
325			`oc8051_b_register oc8051_b_register (.clk(clk),`
326			`.rst(rst),`
327			`.bit_in(bit_in),`
328			`.data_in(des_acc),`
329			`.wr(we),`
330			`.wr_bit(wr_bit_r),`
331			`.wr_addr(adr1),`
332			`.data_out(b_reg));`
333
334			`//`
335			`//stack pointer`
336			`// SP`
337			`oc8051_sp oc8051_sp1(.clk(clk),`
338			`.rst(rst),`
339			`.ram_rd_sel(ram_rd_sel),`
340			`.ram_wr_sel(ram_wr_sel),`
341			`.wr_addr(adr1),`
342			`.wr(we),`
343			`.wr_bit(wr_bit_r),`
344			`.data_in(dat1),`
345			`.sp_out(sp),`
346			`.sp_w(sp_w));`
347
348			`//`
349			`//data pointer`
350			`// DPTR, DPH, DPL`
351			`oc8051_dptr oc8051_dptr1(.clk(clk),`
352			`.rst(rst),`
353			`.addr(adr1),`
354			`.data_in(des_acc),`
355			`.data2_in(dat2),`
356			`.wr(we),`
357			`.wr_bit(wr_bit_r),`
358			`.data_hi(dptr_hi),`
359			`.data_lo(dptr_lo),`
360			`.wr_sfr(wr_sfr));`
361
362
363			`//`
364			`//program status word`
365			`// PSW`
366			`oc8051_psw oc8051_psw1 (.clk(clk),`
367			`.rst(rst),`
368			`.wr_addr(adr1),`
369			`.data_in(dat1),`
370			`.wr(we),`
371			`.wr_bit(wr_bit_r),`
372			`.data_out(psw),`
373			`.p(p),`
374			`.cy_in(bit_in),`
375			`.ac_in(desAc),`
376			`.ov_in(desOv),`
377			`.set(psw_set),`
378			`.bank_sel(bank_sel));`
379
380			`//`
381			`// ports`
382			`// P0, P1, P2, P3`
383			`ifdef OC8051_PORTS
384			`oc8051_ports oc8051_ports1(.clk(clk),`
385			`.rst(rst),`
386			`.bit_in(bit_in),`
387			`.data_in(dat1),`
388			`.wr(we),`
389			`.wr_bit(wr_bit_r),`
390			`.wr_addr(adr1),`
391
392			`ifdef OC8051_PORT0
393			`.p0_out(p0_out),`
394			`.p0_in(p0_in),`
395			`.p0_data(p0_data),`
396			`endif
397
398			`ifdef OC8051_PORT1
399			`.p1_out(p1_out),`
400			`.p1_in(p1_in),`
401			`.p1_data(p1_data),`
402			`endif
403
404			`ifdef OC8051_PORT2
405			`.p2_out(p2_out),`
406			`.p2_in(p2_in),`
407			`.p2_data(p2_data),`
408			`endif
409
410			`ifdef OC8051_PORT3
411			`.p3_out(p3_out),`
412			`.p3_in(p3_in),`
413			`.p3_data(p3_data),`
414			`endif
415
416			`.rmw(rmw));`
417			`endif
418
419			`//`
420			`// serial interface`
421			`// SCON, SBUF`
422			`ifdef OC8051_UART
423			`oc8051_uart oc8051_uatr1 (.clk(clk),`
424			`.rst(rst),`
425			`.bit_in(bit_in),`
426			`.data_in(dat1),`
427			`.wr(we),`
428			`.wr_bit(wr_bit_r),`
429			`.wr_addr(adr1),`
430			`.rxd(rxd),`
431			`.txd(txd),`
432			`// interrupt`
433			`.intr(uart_int),`
434			`// baud rate sources`
435			`.brate2(brate2),`
436			`.t1_ow(tf1),`
437			`.pres_ow(pres_ow),`
438			`.rclk(rclk),`
439			`.tclk(tclk),`
440			`//registers`
441			`.scon(scon),`
442			`.pcon(pcon),`
443			`.sbuf(sbuf));`
444			`else
445			`assign uart_int = 1'b0;`
446			`endif
447
448			`//`
449			`// interrupt control`
450			`// IP, IE, TCON`
451			`oc8051_int oc8051_int1 (.clk(clk),`
452			`.rst(rst),`
453			`.wr_addr(adr1),`
454			`.bit_in(bit_in),`
455			`.ack(int_ack),`
456			`.data_in(dat1),`
457			`.wr(we),`
458			`.wr_bit(wr_bit_r),`
459			`.tf0(tf0),`
460			`.tf1(tf1),`
461			`.t2_int(tc2_int),`
462			`.tr0(tr0),`
463			`.tr1(tr1),`
464			`.ie0(int0),`
465			`.ie1(int1),`
466			`.uart_int(uart_int),`
467			`.reti(reti),`
468			`.intr(intr),`
469			`.int_vec(int_src),`
470			`.ie(ie),`
471			`.tcon(tcon),`
472			`.ip(ip));`
473
474
475			`//`
476			`// timer/counter control`
477			`// TH0, TH1, TL0, TH1, TMOD`
478			`ifdef OC8051_TC01
479			`oc8051_tc oc8051_tc1(.clk(clk),`
480			`.rst(rst),`
481			`.wr_addr(adr1),`
482			`.data_in(dat1),`
483			`.wr(we),`
484			`.wr_bit(wr_bit_r),`
485			`.ie0(int0),`
486			`.ie1(int1),`
487			`.tr0(tr0),`
488			`.tr1(tr1),`
489			`.t0(t0),`
490			`.t1(t1),`
491			`.tf0(tf0),`
492			`.tf1(tf1),`
493			`.pres_ow(pres_ow),`
494			`.tmod(tmod),`
495			`.tl0(tl0),`
496			`.th0(th0),`
497			`.tl1(tl1),`
498			`.th1(th1));`
499			`else
500			`assign tf0 = 1'b0;`
501			`assign tf1 = 1'b0;`
502			`endif
503
504			`//`
505			`// timer/counter 2`
506			`// TH2, TL2, RCAPL2L, RCAPL2H, T2CON`
507			`ifdef OC8051_TC2
508			`oc8051_tc2 oc8051_tc21(.clk(clk),`
509			`.rst(rst),`
510			`.wr_addr(adr1),`
511			`.data_in(dat1),`
512			`.wr(we),`
513			`.wr_bit(wr_bit_r),`
514			`.bit_in(bit_in),`
515			`.t2(t2),`
516			`.t2ex(t2ex),`
517			`.rclk(rclk),`
518			`.tclk(tclk),`
519			`.brate2(brate2),`
520			`.tc2_int(tc2_int),`
521			`.pres_ow(pres_ow),`
522			`.t2con(t2con),`
523			`.tl2(tl2),`
524			`.th2(th2),`
525			`.rcap2l(rcap2l),`
526			`.rcap2h(rcap2h));`
527			`else
528			`assign tc2_int = 1'b0;`
529			`assign rclk = 1'b0;`
530			`assign tclk = 1'b0;`
531			`assign brate2 = 1'b0;`
532			`endif
533
534
535
536			`always @(posedge clk or posedge rst)`
537			`if (rst) begin`
538			`adr0_r <= #1 8'h00;`
539			`ram_wr_sel_r <= #1 3'b000;`
540			`wr_bit_r <= #1 1'b0;`
541			`// wait_data <= #1 1'b0;`
542			`end else begin`
543			`adr0_r <= #1 adr0;`
544			`ram_wr_sel_r <= #1 ram_wr_sel;`
545			`wr_bit_r <= #1 wr_bit;`
546			`end`
547
548			`assign comp_wait = !(`
549			((comp_sel==`OC8051_CSS_AZ) &
550			((wr_sfr==`OC8051_WRS_ACC1) \|
551			(wr_sfr==`OC8051_WRS_ACC2) \|
552			((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) \|
553			((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) \|
554			((comp_sel==`OC8051_CSS_CY) &
555			`((\|psw_set) \|`
556			((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) \|
557			((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) \|
558			((comp_sel==`OC8051_CSS_BIT) &
559			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
560			`((adr1==adr0) & adr1[7] & we & !wr_bit_r)));`
561
562
563
564			`//`
565			`//set output in case of address (byte)`
566			`always @(posedge clk or posedge rst)`
567			`begin`
568			`if (rst) begin`
569			`dat0 <= #1 8'h00;`
570			`wait_data <= #1 1'b0;`
571			end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
572			`dat0 <= #1 des_acc;`
573			`wait_data <= #1 1'b0;`
574			`end else if (`
575			`(`
576			((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
577			// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) \| //write to dpl
578			`(adr1[7] & (adr1==adr0) & we & !wr_bit_r) \| //write and read same address`
579			`(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address`
580			`) & !wait_data) begin`
581			`wait_data <= #1 1'b1;`
582
583			`end else if ((`
584			((\|psw_set) & (adr0==`OC8051_SFR_PSW)) \|
585			((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
586			((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
587			`) & !wait_data) begin`
588			`wait_data <= #1 1'b1;`
589
590			`end else begin`
591			`case (adr0) /* synopsys full_case parallel_case */`
592			`OC8051_SFR_ACC: dat0 <= #1 acc;
593			`OC8051_SFR_PSW: dat0 <= #1 psw;
594
595			`ifdef OC8051_PORTS
596			`ifdef OC8051_PORT0
597			`OC8051_SFR_P0: dat0 <= #1 p0_data;
598			`endif
599
600			`ifdef OC8051_PORT1
601			`OC8051_SFR_P1: dat0 <= #1 p1_data;
602			`endif
603
604			`ifdef OC8051_PORT2
605			`OC8051_SFR_P2: dat0 <= #1 p2_data;
606			`endif
607
608			`ifdef OC8051_PORT3
609			`OC8051_SFR_P3: dat0 <= #1 p3_data;
610			`endif
611			`endif
612
613			`OC8051_SFR_SP: dat0 <= #1 sp;
614			`OC8051_SFR_B: dat0 <= #1 b_reg;
615			`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
616			`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
617
618			`ifdef OC8051_UART
619			`OC8051_SFR_SCON: dat0 <= #1 scon;
620			`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
621			`OC8051_SFR_PCON: dat0 <= #1 pcon;
622			`endif
623
624			`ifdef OC8051_TC01
625			`OC8051_SFR_TH0: dat0 <= #1 th0;
626			`OC8051_SFR_TH1: dat0 <= #1 th1;
627			`OC8051_SFR_TL0: dat0 <= #1 tl0;
628			`OC8051_SFR_TL1: dat0 <= #1 tl1;
629			`OC8051_SFR_TMOD: dat0 <= #1 tmod;
630			`endif
631
632			`OC8051_SFR_IP: dat0 <= #1 ip;
633			`OC8051_SFR_IE: dat0 <= #1 ie;
634			`OC8051_SFR_TCON: dat0 <= #1 tcon;
635
636			`ifdef OC8051_TC2
637			`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
638			`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
639			`OC8051_SFR_TH2: dat0 <= #1 th2;
640			`OC8051_SFR_TL2: dat0 <= #1 tl2;
641			`OC8051_SFR_T2CON: dat0 <= #1 t2con;
642			`endif
643
644			`// default: dat0 <= #1 8'h00;`
645			`endcase`
646			`wait_data <= #1 1'b0;`
647			`end`
648			`end`
649
650
651			`//`
652			`//set output in case of address (bit)`
653
654			`always @(posedge clk or posedge rst)`
655			`begin`
656			`if (rst)`
657			`bit_out <= #1 1'h0;`
658			`else if (`
659			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
660			((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
661			`)`
662
663			`bit_out <= #1 dat1[adr0[2:0]];`
664			`else if ((adr1==adr0) & we & wr_bit_r)`
665			`bit_out <= #1 bit_in;`
666			`else`
667			`case (adr0[7:3]) /* synopsys full_case parallel_case */`
668			`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
669			`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
670
671			`ifdef OC8051_PORTS
672			`ifdef OC8051_PORT0
673			`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
674			`endif
675
676			`ifdef OC8051_PORT1
677			`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
678			`endif
679
680			`ifdef OC8051_PORT2
681			`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
682			`endif
683
684			`ifdef OC8051_PORT3
685			`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
686			`endif
687			`endif
688
689			`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
690			`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
691			`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
692			`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
693
694			`ifdef OC8051_UART
695			`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
696			`endif
697
698			`ifdef OC8051_TC2
699			`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
700			`endif
701
702			`// default: bit_out <= #1 1'b0;`
703			`endcase`
704			`end`
705
706			`always @(posedge clk or posedge rst)`
707			`begin`
708			`if (rst) begin`
709			`prescaler <= #1 4'h0;`
710			`pres_ow <= #1 1'b0;`
711			`end else if (prescaler==4'b1011) begin`
712			`prescaler <= #1 4'h0;`
713			`pres_ow <= #1 1'b1;`
714			`end else begin`
715			`prescaler <= #1 prescaler + 4'h1;`
716			`pres_ow <= #1 1'b0;`
717			`end`
718			`end`
719
720			`endmodule`