URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_sp.v] - Blame information for rev 76

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 stack pointer                                          ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////   8051 special function register: stack pointer.             ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.4  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.3  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "top_defines.v"
 
 
 
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
 
 
input clk, rst, wr, wr_bit;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] data_in, wr_addr;
output [7:0] sp_out, sp_w;
 
reg [7:0] sp_out, sp_w;
reg pop;
wire write;
wire [7:0] sp_t;
 
reg [7:0] sp;
 
 
assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
 
assign sp_t= write ? data_in : sp;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    sp <= #1 `OC8051_RST_SP;
  else if (write)
    sp <= #1 data_in;
  else
    sp <= #1 sp_out;
end
 
 
always @(sp or ram_wr_sel)
begin
//
// push
  if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
  else sp_w = sp;
 
end
 
 
always @(sp_t or ram_wr_sel or pop or write)
begin
//
// push
  if (write) sp_out = sp_t;
  else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
  else sp_out = sp_t - {7'b0, pop};
 
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    pop <= #1 1'b0;
  else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
  else pop <= #1 1'b0;
end
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 stack pointer ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6	76	dinesha	`//// http://www.opencores.org/cores/turbo8051/ ////`
7	2	dinesha	`//// ////`
8			`//// Description ////`
9			`//// 8051 special function register: stack pointer. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16	76	dinesha	`//// - Dinesh Annayya, dinesha@opencores.org ////`
17	2	dinesha	`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.5 2003/01/13 14:14:41 simont`
49			`// replace some modules`
50			`//`
51			`// Revision 1.4 2002/11/05 17:23:54 simont`
52			`// add module oc8051_sfr, 256 bytes internal ram`
53			`//`
54			`// Revision 1.3 2002/09/30 17:33:59 simont`
55			`// prepared header`
56			`//`
57			`//`
58
59	76	dinesha	`include "top_defines.v"
60	2	dinesha
61
62
63			`module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);`
64
65
66			`input clk, rst, wr, wr_bit;`
67			`input [2:0] ram_rd_sel, ram_wr_sel;`
68			`input [7:0] data_in, wr_addr;`
69			`output [7:0] sp_out, sp_w;`
70
71			`reg [7:0] sp_out, sp_w;`
72			`reg pop;`
73			`wire write;`
74			`wire [7:0] sp_t;`
75
76			`reg [7:0] sp;`
77
78
79			assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
80
81			`assign sp_t= write ? data_in : sp;`
82
83
84			`always @(posedge clk or posedge rst)`
85			`begin`
86			`if (rst)`
87			sp <= #1 `OC8051_RST_SP;
88			`else if (write)`
89			`sp <= #1 data_in;`
90			`else`
91			`sp <= #1 sp_out;`
92			`end`
93
94
95			`always @(sp or ram_wr_sel)`
96			`begin`
97			`//`
98			`// push`
99			if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
100			`else sp_w = sp;`
101
102			`end`
103
104
105			`always @(sp_t or ram_wr_sel or pop or write)`
106			`begin`
107			`//`
108			`// push`
109			`if (write) sp_out = sp_t;`
110			else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
111			`else sp_out = sp_t - {7'b0, pop};`
112
113			`end`
114
115
116			`always @(posedge clk or posedge rst)`
117			`begin`
118			`if (rst)`
119			`pop <= #1 1'b0;`
120			else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
121			`else pop <= #1 1'b0;`
122			`end`
123
124			`endmodule`

Browse

Tools

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_sp.v] - Blame information for rev 76