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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_tc.v] - Blame information for rev 27

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores timer/counter control                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   timers and counters handling for 8051 core                 ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/04 10:34:13  simont
// change timers to meet timing specifications (add divider with 12)
//
// Revision 1.5  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.4  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_tc (clk, rst,
            data_in,
            wr_addr,
            wr, wr_bit,
            ie0, ie1,
            tr0, tr1,
            t0, t1,
            tf0, tf1,
            pres_ow,
//registers
            tmod, tl0, th0, tl1, th1);
 
input [7:0]  wr_addr,
             data_in;
input        clk,
             rst,
             wr,
             wr_bit,
             ie0,
             ie1,
             tr0,
             tr1,
             t0,
             t1,
             pres_ow;
output [7:0] tmod,
             tl0,
             th0,
             tl1,
             th1;
output       tf0,
             tf1;
 
 
reg [7:0] tmod, tl0, th0, tl1, th1;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & ((!tmod[2] & pres_ow) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & ((!tmod[6] & pres_ow) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tmod <=#1 `OC8051_RST_TMOD;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
    tmod <= #1 data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl0 <=#1 `OC8051_RST_TL0;
   th0 <=#1 `OC8051_RST_TH0;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
   tl0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
   th0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else begin
     case (tmod[1:0]) /* synopsys full_case parallel_case */
      `OC8051_MODE0: begin                       // mode 0
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        tf1_0 <= #1 1'b0;
        if (tc0_add) begin
          if (tl0 == 8'b1111_1111) begin
            tf0 <=#1 1'b1;
            tl0 <=#1 th0;
           end
          else begin
            tl0 <=#1 tl0 + 8'h1;
            tf0 <= #1 1'b0;
          end
        end
      end
      `OC8051_MODE3: begin                       // mode 3
 
         if (tc0_add)
           {tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
 
         if (tr1 & pres_ow)
           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
 
      end
/*      default:begin
        tf0 <= #1 1'b0;
        tf1_0 <= #1 1'b0;
      end*/
    endcase
 end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl1 <=#1 `OC8051_RST_TL1;
   th1 <=#1 `OC8051_RST_TH1;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
   tl1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
   th1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else begin
     case (tmod[5:4]) /* synopsys full_case parallel_case */
      `OC8051_MODE0: begin                       // mode 0
        if (tc1_add)
          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        if (tc1_add)
          {tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        if (tc1_add) begin
          if (tl1 == 8'b1111_1111) begin
            tf1_1 <=#1 1'b1;
            tl1 <=#1 th1;
           end
          else begin
            tl1 <=#1 tl1 + 8'h1;
            tf1_1 <= #1 1'b0;
          end
        end
      end
/*      default:begin
        tf1_1 <= #1 1'b0;
      end*/
    endcase
 end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    t0_buff <= #1 1'b0;
    t1_buff <= #1 1'b0;
  end else begin
    t0_buff <= #1 t0;
    t1_buff <= #1 t1;
  end
endmodule

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Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_tc.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores timer/counter control ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// timers and counters handling for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.8 2003/04/10 12:43:19 simont`
48			`// defines for pherypherals added`
49			`//`
50			`// Revision 1.7 2003/04/07 14:58:02 simont`
51			`// change sfr's interface.`
52			`//`
53			`// Revision 1.6 2003/04/04 10:34:13 simont`
54			`// change timers to meet timing specifications (add divider with 12)`
55			`//`
56			`// Revision 1.5 2003/01/13 14:14:41 simont`
57			`// replace some modules`
58			`//`
59			`// Revision 1.4 2002/09/30 17:33:59 simont`
60			`// prepared header`
61			`//`
62			`//`
63
64			`include "oc8051_defines.v"
65
66			`//synopsys translate_off`
67			`include "oc8051_timescale.v"
68			`//synopsys translate_on`
69
70
71
72			`module oc8051_tc (clk, rst,`
73			`data_in,`
74			`wr_addr,`
75			`wr, wr_bit,`
76			`ie0, ie1,`
77			`tr0, tr1,`
78			`t0, t1,`
79			`tf0, tf1,`
80			`pres_ow,`
81			`//registers`
82			`tmod, tl0, th0, tl1, th1);`
83
84			`input [7:0] wr_addr,`
85			`data_in;`
86			`input clk,`
87			`rst,`
88			`wr,`
89			`wr_bit,`
90			`ie0,`
91			`ie1,`
92			`tr0,`
93			`tr1,`
94			`t0,`
95			`t1,`
96			`pres_ow;`
97			`output [7:0] tmod,`
98			`tl0,`
99			`th0,`
100			`tl1,`
101			`th1;`
102			`output tf0,`
103			`tf1;`
104
105
106			`reg [7:0] tmod, tl0, th0, tl1, th1;`
107			`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`
108
109			`wire tc0_add, tc1_add;`
110
111			`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & ((!tmod[2] & pres_ow) \| (tmod[2] & !t0 & t0_buff)));`
112			`assign tc1_add = (tr1 & (!tmod[7] \| !ie1) & ((!tmod[6] & pres_ow) \| (tmod[6] & !t1 & t1_buff)));`
113			`assign tf1= tf1_0 \| tf1_1;`
114
115			`//`
116			`// read or write from one of the addresses in tmod`
117			`//`
118			`always @(posedge clk or posedge rst)`
119			`begin`
120			`if (rst) begin`
121			tmod <=#1 `OC8051_RST_TMOD;
122			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
123			`tmod <= #1 data_in;`
124			`end`
125
126			`//`
127			`// TIMER COUNTER 0`
128			`//`
129			`always @(posedge clk or posedge rst)`
130			`begin`
131			`if (rst) begin`
132			tl0 <=#1 `OC8051_RST_TL0;
133			th0 <=#1 `OC8051_RST_TH0;
134			`tf0 <= #1 1'b0;`
135			`tf1_0 <= #1 1'b0;`
136			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
137			`tl0 <= #1 data_in;`
138			`tf0 <= #1 1'b0;`
139			`tf1_0 <= #1 1'b0;`
140			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
141			`th0 <= #1 data_in;`
142			`tf0 <= #1 1'b0;`
143			`tf1_0 <= #1 1'b0;`
144			`end else begin`
145			`case (tmod[1:0]) /* synopsys full_case parallel_case */`
146			`OC8051_MODE0: begin // mode 0
147			`tf1_0 <= #1 1'b0;`
148			`if (tc0_add)`
149			`{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;`
150			`end`
151			`OC8051_MODE1: begin // mode 1
152			`tf1_0 <= #1 1'b0;`
153			`if (tc0_add)`
154			`{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;`
155			`end`
156
157			`OC8051_MODE2: begin // mode 2
158			`tf1_0 <= #1 1'b0;`
159			`if (tc0_add) begin`
160			`if (tl0 == 8'b1111_1111) begin`
161			`tf0 <=#1 1'b1;`
162			`tl0 <=#1 th0;`
163			`end`
164			`else begin`
165			`tl0 <=#1 tl0 + 8'h1;`
166			`tf0 <= #1 1'b0;`
167			`end`
168			`end`
169			`end`
170			`OC8051_MODE3: begin // mode 3
171
172			`if (tc0_add)`
173			`{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;`
174
175			`if (tr1 & pres_ow)`
176			`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`
177
178			`end`
179			`/* default:begin`
180			`tf0 <= #1 1'b0;`
181			`tf1_0 <= #1 1'b0;`
182			`end*/`
183			`endcase`
184			`end`
185			`end`
186
187			`//`
188			`// TIMER COUNTER 1`
189			`//`
190			`always @(posedge clk or posedge rst)`
191			`begin`
192			`if (rst) begin`
193			tl1 <=#1 `OC8051_RST_TL1;
194			th1 <=#1 `OC8051_RST_TH1;
195			`tf1_1 <= #1 1'b0;`
196			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
197			`tl1 <= #1 data_in;`
198			`tf1_1 <= #1 1'b0;`
199			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
200			`th1 <= #1 data_in;`
201			`tf1_1 <= #1 1'b0;`
202			`end else begin`
203			`case (tmod[5:4]) /* synopsys full_case parallel_case */`
204			`OC8051_MODE0: begin // mode 0
205			`if (tc1_add)`
206			`{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;`
207			`end`
208			`OC8051_MODE1: begin // mode 1
209			`if (tc1_add)`
210			`{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;`
211			`end`
212
213			`OC8051_MODE2: begin // mode 2
214			`if (tc1_add) begin`
215			`if (tl1 == 8'b1111_1111) begin`
216			`tf1_1 <=#1 1'b1;`
217			`tl1 <=#1 th1;`
218			`end`
219			`else begin`
220			`tl1 <=#1 tl1 + 8'h1;`
221			`tf1_1 <= #1 1'b0;`
222			`end`
223			`end`
224			`end`
225			`/* default:begin`
226			`tf1_1 <= #1 1'b0;`
227			`end*/`
228			`endcase`
229			`end`
230			`end`
231
232
233			`always @(posedge clk or posedge rst)`
234			`if (rst) begin`
235			`t0_buff <= #1 1'b0;`
236			`t1_buff <= #1 1'b0;`
237			`end else begin`
238			`t0_buff <= #1 t0;`
239			`t1_buff <= #1 t1;`
240			`end`
241			`endmodule`