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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_tc2.v] - Blame information for rev 76

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores timer/counter2 control                           ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////   timers and counters 2 8051 core                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2003/04/04 10:34:13  simont
// change timers to meet timing specifications (add divider with 12)
//
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
//
 
`include "top_defines.v"
 
 
 
module oc8051_tc2 (clk, rst,
            wr_addr,
            data_in, bit_in,
            wr, wr_bit,
            t2, t2ex,
            rclk, tclk,
            brate2, tc2_int,
            pres_ow,
//registers
            t2con, tl2, th2, rcap2l, rcap2h);
 
input [7:0]  wr_addr,
             data_in;
input        clk,
             rst,
             wr,
             wr_bit,
             t2,
             t2ex,
             bit_in,
             pres_ow;   //prescalre owerflov
output [7:0] t2con,
             tl2,
             th2,
             rcap2l,
             rcap2h;
output       tc2_int,
             rclk,
             tclk,
             brate2;
 
 
reg brate2;
reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;
 
reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
 
wire run;
 
//
// t2con
wire tf2, exf2, exen2, tr2, ct2, cprl2;
 
assign tc2_int = tf2 | exf2;
assign tf2   = t2con[7];
assign exf2  = t2con[6];
assign rclk  = t2con[5];
assign tclk  = t2con[4];
assign exen2 = t2con[3];
assign tr2   = t2con[2];
assign ct2   = t2con[1];
assign cprl2 = t2con[0];
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    t2con <= #1 `OC8051_RST_T2CON;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
    t2con <= #1 data_in;
  end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
    t2con[wr_addr[2:0]] <= #1 bit_in;
  end else if (tf2_set) begin
    t2con[7] <= #1 1'b1;
  end else if (exen2 & neg_trans) begin
    t2con[6] <= #1 1'b1;
  end
end
 
 
//
//th2, tl2
assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
//
// reset
//
    tl2 <= #1 `OC8051_RST_TL2;
    th2 <= #1 `OC8051_RST_TH2;
    brate2 <= #1 1'b0;
    tf2_set <= #1 1'b0;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
//
// write to timer 2 high
//
    th2 <= #1 data_in;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
//
// write to timer 2 low
//
    tl2 <= #1 data_in;
  end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
//
// avto reload mode, exen2=1, 0-1 transition on t2ex pin
//
    th2 <= #1 rcap2h;
    tl2 <= #1 rcap2l;
    tf2_set <= #1 1'b0;
  end else if (run) begin
    if (rclk | tclk) begin
//
// boud rate generator mode
//
      if (&{th2, tl2}) begin
        th2 <= #1 rcap2h;
        tl2 <= #1 rcap2l;
        brate2 <= #1 1'b1;
      end else begin
        {brate2, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
      end
      tf2_set <= #1 1'b0;
    end else if (cprl2) begin
//
// capture mode
//
      {tf2_set, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
    end else begin
//
// auto reload mode
//
      if (&{th2, tl2}) begin
        th2 <= #1 rcap2h;
        tl2 <= #1 rcap2l;
        tf2_set <= #1 1'b1;
      end else begin
        {tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
      end
    end
  end else tf2_set <= #1 1'b0;
end
 
 
//
// rcap2l, rcap2h
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    rcap2l <= #1 `OC8051_RST_RCAP2L;
    rcap2h <= #1 `OC8051_RST_RCAP2H;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
    rcap2h <= #1 data_in;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
    rcap2l <= #1 data_in;
  end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin
    rcap2l <= #1 tl2;
    rcap2h <= #1 th2;
  end
end
 
 
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    neg_trans <= #1 1'b0;
    t2ex_r <= #1 1'b0;
  end else if (t2ex) begin
    neg_trans <= #1 1'b0;
    t2ex_r <= #1 1'b1;
  end else if (t2ex_r) begin
    neg_trans <= #1 1'b1;
    t2ex_r <= #1 1'b0;
  end else begin
    neg_trans <= #1 1'b0;
    t2ex_r <= #1 t2ex_r;
  end
end
 
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    tc2_event <= #1 1'b0;
    t2_r <= #1 1'b0;
  end else if (t2) begin
    tc2_event <= #1 1'b0;
    t2_r <= #1 1'b1;
  end else if (!t2 & t2_r) begin
    tc2_event <= #1 1'b1;
    t2_r <= #1 1'b0;
  end else begin
    tc2_event <= #1 1'b0;
  end
end
 
endmodule

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Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_tc2.v] - Blame information for rev 76

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores timer/counter2 control ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6	76	dinesha	`//// http://www.opencores.org/cores/turbo8051/ ////`
7	2	dinesha	`//// ////`
8			`//// Description ////`
9			`//// timers and counters 2 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16	76	dinesha	`//// - Dinesh Annayya, dinesha@opencores.org ////`
17	2	dinesha	`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.2 2003/04/04 10:34:13 simont`
49			`// change timers to meet timing specifications (add divider with 12)`
50			`//`
51			`// Revision 1.1 2003/01/13 14:13:12 simont`
52			`// initial import`
53			`//`
54			`//`
55			`//`
56
57	76	dinesha	`include "top_defines.v"
58	2	dinesha
59
60
61			`module oc8051_tc2 (clk, rst,`
62			`wr_addr,`
63			`data_in, bit_in,`
64			`wr, wr_bit,`
65			`t2, t2ex,`
66			`rclk, tclk,`
67			`brate2, tc2_int,`
68			`pres_ow,`
69			`//registers`
70			`t2con, tl2, th2, rcap2l, rcap2h);`
71
72			`input [7:0] wr_addr,`
73			`data_in;`
74			`input clk,`
75			`rst,`
76			`wr,`
77			`wr_bit,`
78			`t2,`
79			`t2ex,`
80			`bit_in,`
81			`pres_ow; //prescalre owerflov`
82			`output [7:0] t2con,`
83			`tl2,`
84			`th2,`
85			`rcap2l,`
86			`rcap2h;`
87			`output tc2_int,`
88			`rclk,`
89			`tclk,`
90			`brate2;`
91
92
93			`reg brate2;`
94			`reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;`
95
96			`reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;`
97
98			`wire run;`
99
100			`//`
101			`// t2con`
102			`wire tf2, exf2, exen2, tr2, ct2, cprl2;`
103
104			`assign tc2_int = tf2 \| exf2;`
105			`assign tf2 = t2con[7];`
106			`assign exf2 = t2con[6];`
107			`assign rclk = t2con[5];`
108			`assign tclk = t2con[4];`
109			`assign exen2 = t2con[3];`
110			`assign tr2 = t2con[2];`
111			`assign ct2 = t2con[1];`
112			`assign cprl2 = t2con[0];`
113
114			`always @(posedge clk or posedge rst)`
115			`begin`
116			`if (rst) begin`
117			t2con <= #1 `OC8051_RST_T2CON;
118			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
119			`t2con <= #1 data_in;`
120			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
121			`t2con[wr_addr[2:0]] <= #1 bit_in;`
122			`end else if (tf2_set) begin`
123			`t2con[7] <= #1 1'b1;`
124			`end else if (exen2 & neg_trans) begin`
125			`t2con[6] <= #1 1'b1;`
126			`end`
127			`end`
128
129
130			`//`
131			`//th2, tl2`
132			`assign run = tr2 & ((!ct2 & pres_ow) \| (ct2 & tc2_event));`
133
134			`always @(posedge clk or posedge rst)`
135			`begin`
136			`if (rst) begin`
137			`//`
138			`// reset`
139			`//`
140			tl2 <= #1 `OC8051_RST_TL2;
141			th2 <= #1 `OC8051_RST_TH2;
142			`brate2 <= #1 1'b0;`
143			`tf2_set <= #1 1'b0;`
144			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
145			`//`
146			`// write to timer 2 high`
147			`//`
148			`th2 <= #1 data_in;`
149			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
150			`//`
151			`// write to timer 2 low`
152			`//`
153			`tl2 <= #1 data_in;`
154			`end else if (!(rclk \| tclk) & !cprl2 & exen2 & neg_trans) begin`
155			`//`
156			`// avto reload mode, exen2=1, 0-1 transition on t2ex pin`
157			`//`
158			`th2 <= #1 rcap2h;`
159			`tl2 <= #1 rcap2l;`
160			`tf2_set <= #1 1'b0;`
161			`end else if (run) begin`
162			`if (rclk \| tclk) begin`
163			`//`
164			`// boud rate generator mode`
165			`//`
166			`if (&{th2, tl2}) begin`
167			`th2 <= #1 rcap2h;`
168			`tl2 <= #1 rcap2l;`
169			`brate2 <= #1 1'b1;`
170			`end else begin`
171			`{brate2, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;`
172			`end`
173			`tf2_set <= #1 1'b0;`
174			`end else if (cprl2) begin`
175			`//`
176			`// capture mode`
177			`//`
178			`{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;`
179			`end else begin`
180			`//`
181			`// auto reload mode`
182			`//`
183			`if (&{th2, tl2}) begin`
184			`th2 <= #1 rcap2h;`
185			`tl2 <= #1 rcap2l;`
186			`tf2_set <= #1 1'b1;`
187			`end else begin`
188			`{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;`
189			`end`
190			`end`
191			`end else tf2_set <= #1 1'b0;`
192			`end`
193
194
195			`//`
196			`// rcap2l, rcap2h`
197			`always @(posedge clk or posedge rst)`
198			`begin`
199			`if (rst) begin`
200			rcap2l <= #1 `OC8051_RST_RCAP2L;
201			rcap2h <= #1 `OC8051_RST_RCAP2H;
202			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
203			`rcap2h <= #1 data_in;`
204			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
205			`rcap2l <= #1 data_in;`
206			`end else if (!(rclk \| tclk) & exen2 & cprl2 & neg_trans) begin`
207			`rcap2l <= #1 tl2;`
208			`rcap2h <= #1 th2;`
209			`end`
210			`end`
211
212
213			`//`
214			`//`
215			`always @(posedge clk or posedge rst)`
216			`begin`
217			`if (rst) begin`
218			`neg_trans <= #1 1'b0;`
219			`t2ex_r <= #1 1'b0;`
220			`end else if (t2ex) begin`
221			`neg_trans <= #1 1'b0;`
222			`t2ex_r <= #1 1'b1;`
223			`end else if (t2ex_r) begin`
224			`neg_trans <= #1 1'b1;`
225			`t2ex_r <= #1 1'b0;`
226			`end else begin`
227			`neg_trans <= #1 1'b0;`
228			`t2ex_r <= #1 t2ex_r;`
229			`end`
230			`end`
231
232			`//`
233			`//`
234			`always @(posedge clk or posedge rst)`
235			`begin`
236			`if (rst) begin`
237			`tc2_event <= #1 1'b0;`
238			`t2_r <= #1 1'b0;`
239			`end else if (t2) begin`
240			`tc2_event <= #1 1'b0;`
241			`t2_r <= #1 1'b1;`
242			`end else if (!t2 & t2_r) begin`
243			`tc2_event <= #1 1'b1;`
244			`t2_r <= #1 1'b0;`
245			`end else begin`
246			`tc2_event <= #1 1'b0;`
247			`end`
248			`end`
249
250			`endmodule`