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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores top level module                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////  8051 definitions.                                           ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.32  2003/06/20 13:36:37  simont
// ram modules added.
//
// Revision 1.31  2003/06/17 14:17:22  simont
// BIST signals added.
//
// Revision 1.30  2003/06/03 16:51:24  simont
// include "8051_defines" added.
//
// Revision 1.29  2003/05/07 12:36:03  simont
// chsnge comp.des to des1
//
// Revision 1.28  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
// Revision 1.27  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.26  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.25  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.24  2003/04/11 10:05:59  simont
// deifne OC8051_ROM added
//
// Revision 1.23  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.22  2003/04/09 16:24:04  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.21  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.20  2003/04/03 19:13:28  simont
// Include instruction cache.
//
// Revision 1.19  2003/04/02 15:08:30  simont
// raname signals.
//
// Revision 1.18  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.17  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.16  2002/10/28 14:55:00  simont
// fix bug in interface to external data ram
//
// Revision 1.15  2002/10/23 16:53:39  simont
// fix bugs in instruction interface
//
// Revision 1.14  2002/10/17 18:50:00  simont
// cahnge interface to instruction rom
//
// Revision 1.13  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_top (wb_rst_i, wb_clk_i,
//interface to instruction rom
                wbi_adr_o,
                wbi_dat_i,
                wbi_stb_o,
                wbi_ack_i,
                wbi_cyc_o,
                wbi_err_i,
 
//interface to data ram
                wbd_dat_i,
                wbd_dat_o,
                wbd_adr_o,
                wbd_we_o,
                wbd_ack_i,
                wbd_stb_o,
                wbd_cyc_o,
                wbd_err_i,
 
// interrupt interface
                int0_i,
                int1_i,
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
                p0_i,
                p0_o,
        `endif
 
        `ifdef OC8051_PORT1
                p1_i,
                p1_o,
        `endif
 
        `ifdef OC8051_PORT2
                p2_i,
                p2_o,
        `endif
 
        `ifdef OC8051_PORT3
                p3_i,
                p3_o,
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
                rxd_i, txd_o,
        `endif
 
// counter interface
        `ifdef OC8051_TC01
                t0_i, t1_i,
        `endif
 
        `ifdef OC8051_TC2
                t2_i, t2ex_i,
        `endif
 
// BIST
`ifdef OC8051_BIST
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en,
`endif
// external access (active low)
                ea_in
                );
 
 
 
input         wb_rst_i,         // reset input
              wb_clk_i,         // clock input
              int0_i,           // interrupt 0
              int1_i,           // interrupt 1
              ea_in,            // external access
              wbd_ack_i,        // data acknowalge
              wbi_ack_i,        // instruction acknowlage
              wbd_err_i,        // data error
              wbi_err_i;        // instruction error
 
input [7:0]   wbd_dat_i;        // ram data input
input [31:0]  wbi_dat_i;        // rom data input
 
output        wbd_we_o,         // data write enable
              wbd_stb_o,        // data strobe
              wbd_cyc_o,        // data cycle
              wbi_stb_o,        // instruction strobe
              wbi_cyc_o;        // instruction cycle
 
output [7:0]  wbd_dat_o;        // data output
 
output [15:0] wbd_adr_o,        // data address
              wbi_adr_o;        // instruction address
 
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0]  p0_i;             // port 0 input
output [7:0]  p0_o;             // port 0 output
`endif
 
`ifdef OC8051_PORT1
input  [7:0]  p1_i;             // port 1 input
output [7:0]  p1_o;             // port 1 output
`endif
 
`ifdef OC8051_PORT2
input  [7:0]  p2_i;             // port 2 input
output [7:0]  p2_o;             // port 2 output
`endif
 
`ifdef OC8051_PORT3
input  [7:0]  p3_i;             // port 3 input
output [7:0]  p3_o;             // port 3 output
`endif
 
`endif
 
 
 
 
 
 
`ifdef OC8051_UART
input         rxd_i;            // receive
output        txd_o;            // transnmit
`endif
 
`ifdef OC8051_TC01
input         t0_i,             // counter 0 input
              t1_i;             // counter 1 input
`endif
 
`ifdef OC8051_TC2
input         t2_i,             // counter 2 input
              t2ex_i;           //
`endif
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
wire    scanb_soi;
`endif
 
wire [7:0]  dptr_hi,
            dptr_lo,
            ri,
            data_out,
            op1,
            op2,
            op3,
            acc,
            p0_out,
            p1_out,
            p2_out,
            p3_out,
            sp,
            sp_w;
 
wire [31:0] idat_onchip;
 
wire [15:0] pc;
 
assign wbd_cyc_o = wbd_stb_o;
 
wire        src_sel3;
wire [1:0]  wr_sfr,
            src_sel2;
wire [2:0]  ram_rd_sel, // ram read
            ram_wr_sel, // ram write
            src_sel1;
 
wire [7:0]  ram_data,
            ram_out,    //data from ram
            sfr_out,
            wr_dat,
            wr_addr,    //ram write addres
            rd_addr;    //data ram read addres
wire        sfr_bit;
 
wire [1:0]  cy_sel,     //carry select; from decoder to cy_selct1
            bank_sel;
wire        rom_addr_sel,       //rom addres select; alu or pc
            rmw,
            ea_int;
 
wire        reti,
            intr,
            int_ack,
            istb;
wire [7:0]  int_src;
 
wire        mem_wait;
wire [2:0]  mem_act;
wire [3:0]  alu_op;     //alu operation (from decoder)
wire [1:0]  psw_set;    //write to psw or not; from decoder to psw (through register)
 
wire [7:0]  src1,       //alu sources 1
            src2,       //alu sources 2
            src3,       //alu sources 3
            des_acc,
            des1,       //alu destination 1
            des2;       //alu destinations 2
wire        desCy,      //carry out
            desAc,
            desOv,      //overflow
            alu_cy,
            wr,         //write to data ram
            wr_o;
 
wire        rd,         //read program rom
            pc_wr;
wire [2:0]  pc_wr_sel;  //program counter write select (from decoder to pc)
 
wire [7:0]  op1_n, //from memory_interface to decoder
            op2_n,
            op3_n;
 
wire [1:0]  comp_sel;   //select source1 and source2 to compare
wire        eq,         //result (from comp1 to decoder)
            srcAc,
            cy,
            rd_ind,
            wr_ind,
            comp_wait;
wire [2:0]  op1_cur;
 
wire        bit_addr,   //bit addresable instruction
            bit_data,   //bit data from ram to ram_select
            bit_out,    //bit data from ram_select to alu and cy_select
            bit_addr_o,
            wait_data;
 
//
// cpu to cache/wb_interface
wire        iack_i,
            istb_o,
            icyc_o;
wire [31:0] idat_i;
wire [15:0] iadr_o;
 
 
//
// decoder
oc8051_decoder oc8051_decoder1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .op_in              (op1_n              ),
          .op1_c              (op1_cur            ),
          .ram_rd_sel_o       (ram_rd_sel         ),
          .ram_wr_sel_o       (ram_wr_sel         ),
          .bit_addr           (bit_addr           ),
 
          .src_sel1           (src_sel1           ),
          .src_sel2           (src_sel2           ),
          .src_sel3           (src_sel3           ),
 
          .alu_op_o           (alu_op             ),
          .psw_set            (psw_set            ),
          .cy_sel             (cy_sel             ),
          .wr_o               (wr                 ),
          .pc_wr              (pc_wr              ),
          .pc_sel             (pc_wr_sel          ),
          .comp_sel           (comp_sel           ),
          .eq                 (eq                 ),
          .wr_sfr_o           (wr_sfr             ),
          .rd                 (rd                 ),
          .rmw                (rmw                ),
          .istb               (istb               ),
          .mem_act            (mem_act            ),
          .mem_wait           (mem_wait           ),
          .wait_data          (wait_data          )
     );
 
 
wire [7:0] sub_result;
//
//alu
oc8051_alu oc8051_alu1(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
          .op_code            (alu_op             ),
          .src1               (src1               ),
          .src2               (src2               ),
          .src3               (src3               ),
          .srcCy              (alu_cy             ),
          .srcAc              (srcAc              ),
          .des_acc            (des_acc            ),
          .sub_result         (sub_result         ),
          .des1               (des1               ),
          .des2               (des2               ),
          .desCy              (desCy              ),
          .desAc              (desAc              ),
          .desOv              (desOv              ),
          .bit_in(bit_out)
       );
 
//
//data ram
oc8051_ram_top oc8051_ram_top1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .rd_addr            (rd_addr            ),
          .rd_data            (ram_data           ),
          .wr_addr            (wr_addr            ),
          .bit_addr           (bit_addr_o         ),
          .wr_data            (wr_dat             ),
          .wr                 (wr_o &&
                               (!wr_addr[7] || wr_ind)),
          .bit_data_in        (desCy              ),
          .bit_data_out       (bit_data           )
`ifdef OC8051_BIST
         ,
          .scanb_rst          (scanb_rst          ),
          .scanb_clk          (scanb_clk          ),
          .scanb_si           (scanb_soi          ),
          .scanb_so           (scanb_so           ),
          .scanb_en           (scanb_en           )
`endif
                               );
 
//
 
oc8051_alu_src_sel oc8051_alu_src_sel1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .rd                 (rd                 ),
 
          .sel1               (src_sel1           ),
          .sel2               (src_sel2           ),
          .sel3               (src_sel3           ),
 
          .acc                (acc                ),
          .ram                (ram_out            ),
          .pc                 (pc                 ),
          .dptr               ({dptr_hi, dptr_lo} ),
          .op1                (op1_n              ),
          .op2                (op2_n              ),
          .op3                (op3_n              ),
 
          .src1               (src1               ),
          .src2               (src2               ),
          .src3               (src3               )
      );
 
 
//
//
oc8051_comp oc8051_comp1(
          .sel                (comp_sel           ),
          .eq                 (eq                 ),
          .b_in               (bit_out            ),
          .cy                 (cy                 ),
          .acc                (acc                ),
          .des                (sub_result         )
    );
 
 
//
//program rom
`ifdef OC8051_ROM
  oc8051_rom oc8051_rom1(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
          .ea_int             (ea_int             ),
          .addr               (iadr_o             ),
          .data_o             (idat_onchip        )
     );
`else
  assign ea_int = 1'b0;
  assign idat_onchip = 32'h0;
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      $display("\t * ");
      $display("\t * Internal rom disabled!!!");
      $display("\t * ");
    end
 
  `endif
 
`endif
 
//
//
oc8051_cy_select oc8051_cy_select1(
          .cy_sel             (cy_sel             ),
          .cy_in              (cy                 ),
          .data_in            (bit_out            ),
          .data_out           (alu_cy             )
    );
//
//
oc8051_indi_addr oc8051_indi_addr1 (
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .wr_addr            (wr_addr            ),
          .data_in            (wr_dat             ),
          .wr                 (wr_o               ),
          .wr_bit             (bit_addr_o         ),
          .ri_out             (ri                 ),
          .sel                (op1_cur[0]         ),
          .bank               (bank_sel           )
 );
 
 
 
assign icyc_o = istb_o;
//
//
oc8051_memory_interface oc8051_memory_interface1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
// internal ram
          .wr_i               (wr                 ),
          .wr_o               (wr_o               ),
          .wr_bit_i           (bit_addr           ),
          .wr_bit_o           (bit_addr_o         ),
          .wr_dat             (wr_dat             ),
          .des_acc            (des_acc            ),
          .des1               (des1               ),
          .des2               (des2               ),
          .rd_addr            (rd_addr            ),
          .wr_addr            (wr_addr            ),
          .wr_ind             (wr_ind             ),
          .bit_in             (bit_data           ),
          .in_ram             (ram_data           ),
          .sfr                (sfr_out            ),
          .sfr_bit            (sfr_bit            ),
          .bit_out            (bit_out            ),
          .iram_out           (ram_out            ),
 
// external instrauction rom
          .iack_i             (iack_i             ),
          .iadr_o             (iadr_o             ),
          .idat_i             (idat_i             ),
          .istb_o             (istb_o             ),
 
// internal instruction rom
          .idat_onchip        (idat_onchip        ),
 
// data memory
          .dadr_o             (wbd_adr_o          ),
          .ddat_o             (wbd_dat_o          ),
          .dwe_o              (wbd_we_o           ),
          .dstb_o             (wbd_stb_o          ),
          .ddat_i             (wbd_dat_i          ),
          .dack_i             (wbd_ack_i          ),
 
// from decoder
          .rd_sel             (ram_rd_sel         ),
          .wr_sel             (ram_wr_sel         ),
          .rn                 ({bank_sel, op1_cur}),
          .rd_ind             (rd_ind             ),
          .rd                 (rd                 ),
          .mem_act            (mem_act            ),
          .mem_wait           (mem_wait           ),
 
// external access
          .ea                 (ea_in              ),
          .ea_int             (ea_int             ),
 
// instructions outputs to cpu
          .op1_out            (op1_n              ),
          .op2_out            (op2_n              ),
          .op3_out            (op3_n              ),
 
// interrupt interface
          .intr               (intr               ),
                       .int_v(int_src),
          .int_ack            (int_ack            ),
          .istb               (istb               ),
          .reti               (reti               ),
 
//pc
          .pc_wr_sel          (pc_wr_sel          ),
          .pc_wr              (pc_wr & comp_wait  ),
          .pc                 (pc                 ),
 
// sfr's
          .sp_w               (sp_w               ),
          .dptr               ({dptr_hi, dptr_lo} ),
          .ri                 (ri                 ),
          .acc                (acc                ),
          .sp                 (sp                 )
       );
 
 
//
//
 
oc8051_sfr oc8051_sfr1(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
          .adr0               (rd_addr[7:0]       ),
          .adr1               (wr_addr[7:0]       ),
          .dat0               (sfr_out            ),
          .dat1               (wr_dat             ),
          .dat2               (des2               ),
          .des_acc            (des_acc            ),
          .we                 (wr_o && !wr_ind    ),
          .bit_in             (desCy              ),
          .bit_out            (sfr_bit            ),
          .wr_bit             (bit_addr_o         ),
          .ram_rd_sel         (ram_rd_sel         ),
          .ram_wr_sel         (ram_wr_sel         ),
          .wr_sfr             (wr_sfr             ),
          .comp_sel           (comp_sel           ),
          .comp_wait          (comp_wait          ),
// acc
          .acc                (acc                ),
// sp
          .sp                 (sp                 ),
          .sp_w               (sp_w               ),
// psw
          .bank_sel           (bank_sel           ),
          .desAc              (desAc              ),
          .desOv              (desOv              ),
          .psw_set            (psw_set            ),
          .srcAc              (srcAc              ),
          .cy                 (cy                 ),
// ports
          .rmw                (rmw                ),
 
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_out             (p0_o               ),
          .p0_in              (p0_i               ),
        `endif
 
        `ifdef OC8051_PORT1
          .p1_out             (p1_o               ),
          .p1_in              (p1_i               ),
        `endif
 
        `ifdef OC8051_PORT2
          .p2_out             (p2_o               ),
          .p2_in              (p2_i               ),
        `endif
 
        `ifdef OC8051_PORT3
          .p3_out             (p3_o               ),
          .p3_in              (p3_i               ),
        `endif
  `endif
 
// uart
        `ifdef OC8051_UART
          .rxd                (rxd_i              ),
          .txd                (txd_o              ),
        `endif
 
// int
          .int_ack            (int_ack            ),
          .intr               (intr               ),
          .int0               (int0_i             ),
          .int1               (int1_i             ),
          .reti               (reti               ),
          .int_src            (int_src            ),
 
// t/c 0,1
        `ifdef OC8051_TC01
          .t0                 (t0_i               ),
          .t1                 (t1_i               ),
        `endif
 
// t/c 2
        `ifdef OC8051_TC2
          .t2                 (t2_i               ),
          .t2ex               (t2ex_i             ),
        `endif
 
// dptr
          .dptr_hi            (dptr_hi            ),
          .dptr_lo            (dptr_lo            ),
          .wait_data          (wait_data          )
       );
 
 
 
 
`ifdef OC8051_CACHE
 
 
  oc8051_icache oc8051_icache1(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
  // cpu
          .adr_i              (iadr_o             ),
          .dat_o              (idat_i             ),
          .stb_i              (istb_o             ),
          .ack_o              (iack_i             ),
          .cyc_i              (icyc_o             ),
  // pins
          .dat_i              (wbi_dat_i          ),
          .stb_o              (wbi_stb_o          ),
          .adr_o              (wbi_adr_o          ),
          .ack_i              (wbi_ack_i          ),
          .cyc_o              (wbi_cyc_o          )
`ifdef OC8051_BIST
         ,
          .scanb_rst          (scanb_rst          ),
          .scanb_clk          (scanb_clk          ),
          .scanb_si           (scanb_si           ),
          .scanb_so           (scanb_soi          ),
          .scanb_en           (scanb_en           )
`endif
        );
 
  defparam oc8051_icache1.ADR_WIDTH = 6;  // cache address wihth
  defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
  defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
  defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
 
 
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      #1
      $display("\t * ");
      $display("\t * External rom interface: cache");
      $display("\t * ");
    end
 
  `endif
 
 
 
//
//    no cache
//
`else
 
  `ifdef OC8051_BIST
       assign scanb_soi=scanb_si;
  `endif
 
  `ifdef OC8051_WB
 
    oc8051_wb_iinterface oc8051_wb_iinterface(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
    // cpu
          .adr_i              (iadr_o             ),
          .dat_o              (idat_i             ),
          .stb_i              (istb_o             ),
          .ack_o              (iack_i             ),
          .cyc_i              (icyc_o             ),
    // external rom
          .dat_i              (wbi_dat_i          ),
          .stb_o              (wbi_stb_o          ),
          .adr_o              (wbi_adr_o          ),
          .ack_i              (wbi_ack_i          ),
          .cyc_o              (wbi_cyc_o          )
       );
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      #1
      $display("\t * ");
      $display("\t * External rom interface: WB interface");
      $display("\t * ");
    end
 
  `endif
 
  `else
 
    assign wbi_adr_o = iadr_o    ;
    assign idat_i    = wbi_dat_i ;
    assign wbi_stb_o = 1'b1      ;
    assign iack_i    = wbi_ack_i ;
    assign wbi_cyc_o = 1'b1      ;
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      #1
      $display("\t * ");
      $display("\t * External rom interface: Pipelined interface");
      $display("\t * ");
    end
 
  `endif
 
 
  `endif
 
`endif
 
 
// synopsys translate_on
// Debug Purpose only
// Stack Pointer Push & Pop analysis
reg [7:0]   StackMem[$];
reg  [7:0]  stack_pop;
reg  [7:0]  pushpop_cnt;
 
// Assumption, Both Write and Read access will not be
// possbile in single clock cycle
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
   if(wb_rst_i) begin
      pushpop_cnt = 0;
   end
   else begin
      if(ram_wr_sel==`OC8051_RWS_SP) begin
            StackMem.push_back(wr_dat);
            pushpop_cnt = pushpop_cnt + 1;
      end
      if(ram_rd_sel==`OC8051_RRS_SP) begin
            stack_pop = StackMem.pop_back();
            pushpop_cnt = pushpop_cnt - 1;
            #2  // Add 1ns Delay to take care of Ram Dealy
            if(stack_pop != ram_data) begin
              $display("ERROR: Invalid Stack Pointer Pop Detected, Exp: %x,Rxd:%x",stack_pop,ram_data);
              $stop;
            end
      end
   end
end
 
// synopsys translate_off
 
endmodule

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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Blame information for rev 61

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.32 2003/06/20 13:36:37 simont`
48			`// ram modules added.`
49			`//`
50			`// Revision 1.31 2003/06/17 14:17:22 simont`
51			`// BIST signals added.`
52			`//`
53			`// Revision 1.30 2003/06/03 16:51:24 simont`
54			`// include "8051_defines" added.`
55			`//`
56			`// Revision 1.29 2003/05/07 12:36:03 simont`
57			`// chsnge comp.des to des1`
58			`//`
59			`// Revision 1.28 2003/05/06 09:41:35 simont`
60			`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
61			`//`
62			`// Revision 1.27 2003/05/05 15:46:37 simont`
63			`// add aditional alu destination to solve critical path.`
64			`//`
65			`// Revision 1.26 2003/04/29 11:24:31 simont`
66			`// fix bug in case execution of two data dependent instructions.`
67			`//`
68			`// Revision 1.25 2003/04/25 17:15:51 simont`
69			`// change branch instruction execution (reduse needed clock periods).`
70			`//`
71			`// Revision 1.24 2003/04/11 10:05:59 simont`
72			`// deifne OC8051_ROM added`
73			`//`
74			`// Revision 1.23 2003/04/10 12:43:19 simont`
75			`// defines for pherypherals added`
76			`//`
77			`// Revision 1.22 2003/04/09 16:24:04 simont`
78			`// change wr_sft to 2 bit wire.`
79			`//`
80			`// Revision 1.21 2003/04/09 15:49:42 simont`
81			`// Register oc8051_sfr dato output, add signal wait_data.`
82			`//`
83			`// Revision 1.20 2003/04/03 19:13:28 simont`
84			`// Include instruction cache.`
85			`//`
86			`// Revision 1.19 2003/04/02 15:08:30 simont`
87			`// raname signals.`
88			`//`
89			`// Revision 1.18 2003/01/13 14:14:41 simont`
90			`// replace some modules`
91			`//`
92			`// Revision 1.17 2002/11/05 17:23:54 simont`
93			`// add module oc8051_sfr, 256 bytes internal ram`
94			`//`
95			`// Revision 1.16 2002/10/28 14:55:00 simont`
96			`// fix bug in interface to external data ram`
97			`//`
98			`// Revision 1.15 2002/10/23 16:53:39 simont`
99			`// fix bugs in instruction interface`
100			`//`
101			`// Revision 1.14 2002/10/17 18:50:00 simont`
102			`// cahnge interface to instruction rom`
103			`//`
104			`// Revision 1.13 2002/09/30 17:33:59 simont`
105			`// prepared header`
106			`//`
107			`//`
108
109			`// synopsys translate_off`
110			`include "oc8051_timescale.v"
111			`// synopsys translate_on`
112
113			`include "oc8051_defines.v"
114
115			`module oc8051_top (wb_rst_i, wb_clk_i,`
116			`//interface to instruction rom`
117			`wbi_adr_o,`
118			`wbi_dat_i,`
119			`wbi_stb_o,`
120			`wbi_ack_i,`
121			`wbi_cyc_o,`
122			`wbi_err_i,`
123
124			`//interface to data ram`
125			`wbd_dat_i,`
126			`wbd_dat_o,`
127			`wbd_adr_o,`
128			`wbd_we_o,`
129			`wbd_ack_i,`
130			`wbd_stb_o,`
131			`wbd_cyc_o,`
132			`wbd_err_i,`
133
134			`// interrupt interface`
135			`int0_i,`
136			`int1_i,`
137
138
139			`// port interface`
140			`ifdef OC8051_PORTS
141			`ifdef OC8051_PORT0
142			`p0_i,`
143			`p0_o,`
144			`endif
145
146			`ifdef OC8051_PORT1
147			`p1_i,`
148			`p1_o,`
149			`endif
150
151			`ifdef OC8051_PORT2
152			`p2_i,`
153			`p2_o,`
154			`endif
155
156			`ifdef OC8051_PORT3
157			`p3_i,`
158			`p3_o,`
159			`endif
160			`endif
161
162			`// serial interface`
163			`ifdef OC8051_UART
164			`rxd_i, txd_o,`
165			`endif
166
167			`// counter interface`
168			`ifdef OC8051_TC01
169			`t0_i, t1_i,`
170			`endif
171
172			`ifdef OC8051_TC2
173			`t2_i, t2ex_i,`
174			`endif
175
176			`// BIST`
177			`ifdef OC8051_BIST
178			`scanb_rst,`
179			`scanb_clk,`
180			`scanb_si,`
181			`scanb_so,`
182			`scanb_en,`
183			`endif
184			`// external access (active low)`
185			`ea_in`
186			`);`
187
188
189
190			`input wb_rst_i, // reset input`
191			`wb_clk_i, // clock input`
192			`int0_i, // interrupt 0`
193			`int1_i, // interrupt 1`
194			`ea_in, // external access`
195			`wbd_ack_i, // data acknowalge`
196			`wbi_ack_i, // instruction acknowlage`
197			`wbd_err_i, // data error`
198			`wbi_err_i; // instruction error`
199
200			`input [7:0] wbd_dat_i; // ram data input`
201			`input [31:0] wbi_dat_i; // rom data input`
202
203			`output wbd_we_o, // data write enable`
204			`wbd_stb_o, // data strobe`
205			`wbd_cyc_o, // data cycle`
206			`wbi_stb_o, // instruction strobe`
207			`wbi_cyc_o; // instruction cycle`
208
209			`output [7:0] wbd_dat_o; // data output`
210
211			`output [15:0] wbd_adr_o, // data address`
212			`wbi_adr_o; // instruction address`
213
214			`ifdef OC8051_PORTS
215
216			`ifdef OC8051_PORT0
217			`input [7:0] p0_i; // port 0 input`
218			`output [7:0] p0_o; // port 0 output`
219			`endif
220
221			`ifdef OC8051_PORT1
222			`input [7:0] p1_i; // port 1 input`
223			`output [7:0] p1_o; // port 1 output`
224			`endif
225
226			`ifdef OC8051_PORT2
227			`input [7:0] p2_i; // port 2 input`
228			`output [7:0] p2_o; // port 2 output`
229			`endif
230
231			`ifdef OC8051_PORT3
232			`input [7:0] p3_i; // port 3 input`
233			`output [7:0] p3_o; // port 3 output`
234			`endif
235
236			`endif
237
238
239
240
241
242
243			`ifdef OC8051_UART
244			`input rxd_i; // receive`
245			`output txd_o; // transnmit`
246			`endif
247
248			`ifdef OC8051_TC01
249			`input t0_i, // counter 0 input`
250			`t1_i; // counter 1 input`
251			`endif
252
253			`ifdef OC8051_TC2
254			`input t2_i, // counter 2 input`
255			`t2ex_i; //`
256			`endif
257
258			`ifdef OC8051_BIST
259			`input scanb_rst;`
260			`input scanb_clk;`
261			`input scanb_si;`
262			`output scanb_so;`
263			`input scanb_en;`
264			`wire scanb_soi;`
265			`endif
266
267			`wire [7:0] dptr_hi,`
268			`dptr_lo,`
269			`ri,`
270			`data_out,`
271			`op1,`
272			`op2,`
273			`op3,`
274			`acc,`
275			`p0_out,`
276			`p1_out,`
277			`p2_out,`
278			`p3_out,`
279			`sp,`
280			`sp_w;`
281
282			`wire [31:0] idat_onchip;`
283
284			`wire [15:0] pc;`
285
286			`assign wbd_cyc_o = wbd_stb_o;`
287
288			`wire src_sel3;`
289			`wire [1:0] wr_sfr,`
290			`src_sel2;`
291			`wire [2:0] ram_rd_sel, // ram read`
292			`ram_wr_sel, // ram write`
293			`src_sel1;`
294
295			`wire [7:0] ram_data,`
296			`ram_out, //data from ram`
297			`sfr_out,`
298			`wr_dat,`
299			`wr_addr, //ram write addres`
300			`rd_addr; //data ram read addres`
301			`wire sfr_bit;`
302
303			`wire [1:0] cy_sel, //carry select; from decoder to cy_selct1`
304			`bank_sel;`
305			`wire rom_addr_sel, //rom addres select; alu or pc`
306			`rmw,`
307			`ea_int;`
308
309			`wire reti,`
310			`intr,`
311			`int_ack,`
312			`istb;`
313			`wire [7:0] int_src;`
314
315			`wire mem_wait;`
316			`wire [2:0] mem_act;`
317			`wire [3:0] alu_op; //alu operation (from decoder)`
318			`wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)`
319
320			`wire [7:0] src1, //alu sources 1`
321			`src2, //alu sources 2`
322			`src3, //alu sources 3`
323			`des_acc,`
324			`des1, //alu destination 1`
325			`des2; //alu destinations 2`
326			`wire desCy, //carry out`
327			`desAc,`
328			`desOv, //overflow`
329			`alu_cy,`
330			`wr, //write to data ram`
331			`wr_o;`
332
333			`wire rd, //read program rom`
334			`pc_wr;`
335			`wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)`
336
337			`wire [7:0] op1_n, //from memory_interface to decoder`
338			`op2_n,`
339			`op3_n;`
340
341			`wire [1:0] comp_sel; //select source1 and source2 to compare`
342			`wire eq, //result (from comp1 to decoder)`
343			`srcAc,`
344			`cy,`
345			`rd_ind,`
346			`wr_ind,`
347			`comp_wait;`
348			`wire [2:0] op1_cur;`
349
350			`wire bit_addr, //bit addresable instruction`
351			`bit_data, //bit data from ram to ram_select`
352			`bit_out, //bit data from ram_select to alu and cy_select`
353			`bit_addr_o,`
354			`wait_data;`
355
356			`//`
357			`// cpu to cache/wb_interface`
358			`wire iack_i,`
359			`istb_o,`
360			`icyc_o;`
361			`wire [31:0] idat_i;`
362			`wire [15:0] iadr_o;`
363
364
365			`//`
366			`// decoder`
367			`oc8051_decoder oc8051_decoder1(`
368			`.clk (wb_clk_i ),`
369			`.rst (wb_rst_i ),`
370			`.op_in (op1_n ),`
371			`.op1_c (op1_cur ),`
372			`.ram_rd_sel_o (ram_rd_sel ),`
373			`.ram_wr_sel_o (ram_wr_sel ),`
374			`.bit_addr (bit_addr ),`
375
376			`.src_sel1 (src_sel1 ),`
377			`.src_sel2 (src_sel2 ),`
378			`.src_sel3 (src_sel3 ),`
379
380			`.alu_op_o (alu_op ),`
381			`.psw_set (psw_set ),`
382			`.cy_sel (cy_sel ),`
383			`.wr_o (wr ),`
384			`.pc_wr (pc_wr ),`
385			`.pc_sel (pc_wr_sel ),`
386			`.comp_sel (comp_sel ),`
387			`.eq (eq ),`
388			`.wr_sfr_o (wr_sfr ),`
389			`.rd (rd ),`
390			`.rmw (rmw ),`
391			`.istb (istb ),`
392			`.mem_act (mem_act ),`
393			`.mem_wait (mem_wait ),`
394			`.wait_data (wait_data )`
395			`);`
396
397
398			`wire [7:0] sub_result;`
399			`//`
400			`//alu`
401			`oc8051_alu oc8051_alu1(`
402			`.rst (wb_rst_i ),`
403			`.clk (wb_clk_i ),`
404			`.op_code (alu_op ),`
405			`.src1 (src1 ),`
406			`.src2 (src2 ),`
407			`.src3 (src3 ),`
408			`.srcCy (alu_cy ),`
409			`.srcAc (srcAc ),`
410			`.des_acc (des_acc ),`
411			`.sub_result (sub_result ),`
412			`.des1 (des1 ),`
413			`.des2 (des2 ),`
414			`.desCy (desCy ),`
415			`.desAc (desAc ),`
416			`.desOv (desOv ),`
417			`.bit_in(bit_out)`
418			`);`
419
420			`//`
421			`//data ram`
422			`oc8051_ram_top oc8051_ram_top1(`
423			`.clk (wb_clk_i ),`
424			`.rst (wb_rst_i ),`
425			`.rd_addr (rd_addr ),`
426			`.rd_data (ram_data ),`
427			`.wr_addr (wr_addr ),`
428			`.bit_addr (bit_addr_o ),`
429			`.wr_data (wr_dat ),`
430			`.wr (wr_o &&`
431			`(!wr_addr[7] \|\| wr_ind)),`
432			`.bit_data_in (desCy ),`
433			`.bit_data_out (bit_data )`
434			`ifdef OC8051_BIST
435			`,`
436			`.scanb_rst (scanb_rst ),`
437			`.scanb_clk (scanb_clk ),`
438			`.scanb_si (scanb_soi ),`
439			`.scanb_so (scanb_so ),`
440			`.scanb_en (scanb_en )`
441			`endif
442			`);`
443
444			`//`
445
446			`oc8051_alu_src_sel oc8051_alu_src_sel1(`
447			`.clk (wb_clk_i ),`
448			`.rst (wb_rst_i ),`
449			`.rd (rd ),`
450
451			`.sel1 (src_sel1 ),`
452			`.sel2 (src_sel2 ),`
453			`.sel3 (src_sel3 ),`
454
455			`.acc (acc ),`
456			`.ram (ram_out ),`
457			`.pc (pc ),`
458			`.dptr ({dptr_hi, dptr_lo} ),`
459			`.op1 (op1_n ),`
460			`.op2 (op2_n ),`
461			`.op3 (op3_n ),`
462
463			`.src1 (src1 ),`
464			`.src2 (src2 ),`
465			`.src3 (src3 )`
466			`);`
467
468
469			`//`
470			`//`
471			`oc8051_comp oc8051_comp1(`
472			`.sel (comp_sel ),`
473			`.eq (eq ),`
474			`.b_in (bit_out ),`
475			`.cy (cy ),`
476			`.acc (acc ),`
477			`.des (sub_result )`
478			`);`
479
480
481			`//`
482			`//program rom`
483			`ifdef OC8051_ROM
484			`oc8051_rom oc8051_rom1(`
485			`.rst (wb_rst_i ),`
486			`.clk (wb_clk_i ),`
487			`.ea_int (ea_int ),`
488			`.addr (iadr_o ),`
489			`.data_o (idat_onchip )`
490			`);`
491			`else
492			`assign ea_int = 1'b0;`
493			`assign idat_onchip = 32'h0;`
494
495			`ifdef OC8051_SIMULATION
496
497			`initial`
498			`begin`
499			`$display("\t * ");`
500			`$display("\t * Internal rom disabled!!!");`
501			`$display("\t * ");`
502			`end`
503
504			`endif
505
506			`endif
507
508			`//`
509			`//`
510			`oc8051_cy_select oc8051_cy_select1(`
511			`.cy_sel (cy_sel ),`
512			`.cy_in (cy ),`
513			`.data_in (bit_out ),`
514			`.data_out (alu_cy )`
515			`);`
516			`//`
517			`//`
518			`oc8051_indi_addr oc8051_indi_addr1 (`
519			`.clk (wb_clk_i ),`
520			`.rst (wb_rst_i ),`
521			`.wr_addr (wr_addr ),`
522			`.data_in (wr_dat ),`
523			`.wr (wr_o ),`
524			`.wr_bit (bit_addr_o ),`
525			`.ri_out (ri ),`
526			`.sel (op1_cur[0] ),`
527			`.bank (bank_sel )`
528			`);`
529
530
531
532			`assign icyc_o = istb_o;`
533			`//`
534			`//`
535			`oc8051_memory_interface oc8051_memory_interface1(`
536			`.clk (wb_clk_i ),`
537			`.rst (wb_rst_i ),`
538			`// internal ram`
539			`.wr_i (wr ),`
540			`.wr_o (wr_o ),`
541			`.wr_bit_i (bit_addr ),`
542			`.wr_bit_o (bit_addr_o ),`
543			`.wr_dat (wr_dat ),`
544			`.des_acc (des_acc ),`
545			`.des1 (des1 ),`
546			`.des2 (des2 ),`
547			`.rd_addr (rd_addr ),`
548			`.wr_addr (wr_addr ),`
549			`.wr_ind (wr_ind ),`
550			`.bit_in (bit_data ),`
551			`.in_ram (ram_data ),`
552			`.sfr (sfr_out ),`
553			`.sfr_bit (sfr_bit ),`
554			`.bit_out (bit_out ),`
555			`.iram_out (ram_out ),`
556
557			`// external instrauction rom`
558			`.iack_i (iack_i ),`
559			`.iadr_o (iadr_o ),`
560			`.idat_i (idat_i ),`
561			`.istb_o (istb_o ),`
562
563			`// internal instruction rom`
564			`.idat_onchip (idat_onchip ),`
565
566			`// data memory`
567			`.dadr_o (wbd_adr_o ),`
568			`.ddat_o (wbd_dat_o ),`
569			`.dwe_o (wbd_we_o ),`
570			`.dstb_o (wbd_stb_o ),`
571			`.ddat_i (wbd_dat_i ),`
572			`.dack_i (wbd_ack_i ),`
573
574			`// from decoder`
575			`.rd_sel (ram_rd_sel ),`
576			`.wr_sel (ram_wr_sel ),`
577			`.rn ({bank_sel, op1_cur}),`
578			`.rd_ind (rd_ind ),`
579			`.rd (rd ),`
580			`.mem_act (mem_act ),`
581			`.mem_wait (mem_wait ),`
582
583			`// external access`
584			`.ea (ea_in ),`
585			`.ea_int (ea_int ),`
586
587			`// instructions outputs to cpu`
588			`.op1_out (op1_n ),`
589			`.op2_out (op2_n ),`
590			`.op3_out (op3_n ),`
591
592			`// interrupt interface`
593			`.intr (intr ),`
594			`.int_v(int_src),`
595			`.int_ack (int_ack ),`
596			`.istb (istb ),`
597			`.reti (reti ),`
598
599			`//pc`
600			`.pc_wr_sel (pc_wr_sel ),`
601			`.pc_wr (pc_wr & comp_wait ),`
602			`.pc (pc ),`
603
604			`// sfr's`
605			`.sp_w (sp_w ),`
606			`.dptr ({dptr_hi, dptr_lo} ),`
607			`.ri (ri ),`
608			`.acc (acc ),`
609			`.sp (sp )`
610			`);`
611
612
613			`//`
614			`//`
615
616			`oc8051_sfr oc8051_sfr1(`
617			`.rst (wb_rst_i ),`
618			`.clk (wb_clk_i ),`
619			`.adr0 (rd_addr[7:0] ),`
620			`.adr1 (wr_addr[7:0] ),`
621			`.dat0 (sfr_out ),`
622			`.dat1 (wr_dat ),`
623			`.dat2 (des2 ),`
624			`.des_acc (des_acc ),`
625			`.we (wr_o && !wr_ind ),`
626			`.bit_in (desCy ),`
627			`.bit_out (sfr_bit ),`
628			`.wr_bit (bit_addr_o ),`
629			`.ram_rd_sel (ram_rd_sel ),`
630			`.ram_wr_sel (ram_wr_sel ),`
631			`.wr_sfr (wr_sfr ),`
632			`.comp_sel (comp_sel ),`
633			`.comp_wait (comp_wait ),`
634			`// acc`
635			`.acc (acc ),`
636			`// sp`
637			`.sp (sp ),`
638			`.sp_w (sp_w ),`
639			`// psw`
640			`.bank_sel (bank_sel ),`
641			`.desAc (desAc ),`
642			`.desOv (desOv ),`
643			`.psw_set (psw_set ),`
644			`.srcAc (srcAc ),`
645			`.cy (cy ),`
646			`// ports`
647			`.rmw (rmw ),`
648
649			`ifdef OC8051_PORTS
650			`ifdef OC8051_PORT0
651			`.p0_out (p0_o ),`
652			`.p0_in (p0_i ),`
653			`endif
654
655			`ifdef OC8051_PORT1
656			`.p1_out (p1_o ),`
657			`.p1_in (p1_i ),`
658			`endif
659
660			`ifdef OC8051_PORT2
661			`.p2_out (p2_o ),`
662			`.p2_in (p2_i ),`
663			`endif
664
665			`ifdef OC8051_PORT3
666			`.p3_out (p3_o ),`
667			`.p3_in (p3_i ),`
668			`endif
669			`endif
670
671			`// uart`
672			`ifdef OC8051_UART
673			`.rxd (rxd_i ),`
674			`.txd (txd_o ),`
675			`endif
676
677			`// int`
678			`.int_ack (int_ack ),`
679			`.intr (intr ),`
680			`.int0 (int0_i ),`
681			`.int1 (int1_i ),`
682			`.reti (reti ),`
683			`.int_src (int_src ),`
684
685			`// t/c 0,1`
686			`ifdef OC8051_TC01
687			`.t0 (t0_i ),`
688			`.t1 (t1_i ),`
689			`endif
690
691			`// t/c 2`
692			`ifdef OC8051_TC2
693			`.t2 (t2_i ),`
694			`.t2ex (t2ex_i ),`
695			`endif
696
697			`// dptr`
698			`.dptr_hi (dptr_hi ),`
699			`.dptr_lo (dptr_lo ),`
700			`.wait_data (wait_data )`
701			`);`
702
703
704
705
706			`ifdef OC8051_CACHE
707
708
709			`oc8051_icache oc8051_icache1(`
710			`.rst (wb_rst_i ),`
711			`.clk (wb_clk_i ),`
712			`// cpu`
713			`.adr_i (iadr_o ),`
714			`.dat_o (idat_i ),`
715			`.stb_i (istb_o ),`
716			`.ack_o (iack_i ),`
717			`.cyc_i (icyc_o ),`
718			`// pins`
719			`.dat_i (wbi_dat_i ),`
720			`.stb_o (wbi_stb_o ),`
721			`.adr_o (wbi_adr_o ),`
722			`.ack_i (wbi_ack_i ),`
723			`.cyc_o (wbi_cyc_o )`
724			`ifdef OC8051_BIST
725			`,`
726			`.scanb_rst (scanb_rst ),`
727			`.scanb_clk (scanb_clk ),`
728			`.scanb_si (scanb_si ),`
729			`.scanb_so (scanb_soi ),`
730			`.scanb_en (scanb_en )`
731			`endif
732			`);`
733
734			`defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth`
735			`defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)`
736			`defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH`
737			`defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)`
738
739
740
741			`ifdef OC8051_SIMULATION
742
743			`initial`
744			`begin`
745			`#1`
746			`$display("\t * ");`
747			`$display("\t * External rom interface: cache");`
748			`$display("\t * ");`
749			`end`
750
751			`endif
752
753
754
755			`//`
756			`// no cache`
757			`//`
758			`else
759
760			`ifdef OC8051_BIST
761			`assign scanb_soi=scanb_si;`
762			`endif
763
764			`ifdef OC8051_WB
765
766			`oc8051_wb_iinterface oc8051_wb_iinterface(`
767			`.rst (wb_rst_i ),`
768			`.clk (wb_clk_i ),`
769			`// cpu`
770			`.adr_i (iadr_o ),`
771			`.dat_o (idat_i ),`
772			`.stb_i (istb_o ),`
773			`.ack_o (iack_i ),`
774			`.cyc_i (icyc_o ),`
775			`// external rom`
776			`.dat_i (wbi_dat_i ),`
777			`.stb_o (wbi_stb_o ),`
778			`.adr_o (wbi_adr_o ),`
779			`.ack_i (wbi_ack_i ),`
780			`.cyc_o (wbi_cyc_o )`
781			`);`
782
783			`ifdef OC8051_SIMULATION
784
785			`initial`
786			`begin`
787			`#1`
788			`$display("\t * ");`
789			`$display("\t * External rom interface: WB interface");`
790			`$display("\t * ");`
791			`end`
792
793			`endif
794
795			`else
796
797			`assign wbi_adr_o = iadr_o ;`
798			`assign idat_i = wbi_dat_i ;`
799			`assign wbi_stb_o = 1'b1 ;`
800			`assign iack_i = wbi_ack_i ;`
801			`assign wbi_cyc_o = 1'b1 ;`
802
803			`ifdef OC8051_SIMULATION
804
805			`initial`
806			`begin`
807			`#1`
808			`$display("\t * ");`
809			`$display("\t * External rom interface: Pipelined interface");`
810			`$display("\t * ");`
811			`end`
812
813			`endif
814
815
816			`endif
817
818			`endif
819
820
821	61	dinesha	`// synopsys translate_on`
822			`// Debug Purpose only`
823			`// Stack Pointer Push & Pop analysis`
824			`reg [7:0] StackMem[$];`
825			`reg [7:0] stack_pop;`
826			`reg [7:0] pushpop_cnt;`
827	2	dinesha
828	61	dinesha	`// Assumption, Both Write and Read access will not be`
829			`// possbile in single clock cycle`
830			`always @(posedge wb_clk_i or posedge wb_rst_i)`
831			`begin`
832			`if(wb_rst_i) begin`
833			`pushpop_cnt = 0;`
834			`end`
835			`else begin`
836			if(ram_wr_sel==`OC8051_RWS_SP) begin
837			`StackMem.push_back(wr_dat);`
838			`pushpop_cnt = pushpop_cnt + 1;`
839			`end`
840			if(ram_rd_sel==`OC8051_RRS_SP) begin
841			`stack_pop = StackMem.pop_back();`
842			`pushpop_cnt = pushpop_cnt - 1;`
843			`#2 // Add 1ns Delay to take care of Ram Dealy`
844			`if(stack_pop != ram_data) begin`
845			`$display("ERROR: Invalid Stack Pointer Pop Detected, Exp: %x,Rxd:%x",stack_pop,ram_data);`
846			`$stop;`
847			`end`
848			`end`
849			`end`
850			`end`
851
852			`// synopsys translate_off`
853
854	2	dinesha	`endmodule`