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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Blame information for rev 78

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores top level module                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  8051 definitions.                                           ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.32  2003/06/20 13:36:37  simont
// ram modules added.
//
// Revision 1.31  2003/06/17 14:17:22  simont
// BIST signals added.
//
// Revision 1.30  2003/06/03 16:51:24  simont
// include "8051_defines" added.
//
// Revision 1.29  2003/05/07 12:36:03  simont
// chsnge comp.des to des1
//
// Revision 1.28  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
// Revision 1.27  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.26  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.25  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.24  2003/04/11 10:05:59  simont
// deifne OC8051_ROM added
//
// Revision 1.23  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.22  2003/04/09 16:24:04  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.21  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.20  2003/04/03 19:13:28  simont
// Include instruction cache.
//
// Revision 1.19  2003/04/02 15:08:30  simont
// raname signals.
//
// Revision 1.18  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.17  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.16  2002/10/28 14:55:00  simont
// fix bug in interface to external data ram
//
// Revision 1.15  2002/10/23 16:53:39  simont
// fix bugs in instruction interface
//
// Revision 1.14  2002/10/17 18:50:00  simont
// cahnge interface to instruction rom
//
// Revision 1.13  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "top_defines.v"
 
module oc8051_top (wb_rst_i, wb_clk_i,
//interface to instruction rom
                wbi_adr_o,
                wbi_dat_i,
                wbi_stb_o,
                wbi_ack_i,
                wbi_cyc_o,
                wbi_err_i,
 
//interface to data ram
                wbd_dat_i,
                wbd_dat_o,
                wbd_adr_o,
                wbd_we_o,
                wbd_ack_i,
                wbd_stb_o,
                wbd_cyc_o,
                wbd_err_i,
 
// interrupt interface
                int0_i,
                int1_i,
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
                p0_i,
                p0_o,
        `endif
 
        `ifdef OC8051_PORT1
                p1_i,
                p1_o,
        `endif
 
        `ifdef OC8051_PORT2
                p2_i,
                p2_o,
        `endif
 
        `ifdef OC8051_PORT3
                p3_i,
                p3_o,
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
                rxd_i, txd_o,
        `endif
 
// counter interface
        `ifdef OC8051_TC01
                t0_i, t1_i,
        `endif
 
        `ifdef OC8051_TC2
                t2_i, t2ex_i,
        `endif
 
// BIST
`ifdef OC8051_BIST
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en,
`endif
// external access (active low)
                ea_in
                );
 
 
 
input         wb_rst_i,         // reset input
              wb_clk_i,         // clock input
              int0_i,           // interrupt 0
              int1_i,           // interrupt 1
              ea_in,            // external access
              wbd_ack_i,        // data acknowalge
              wbi_ack_i,        // instruction acknowlage
              wbd_err_i,        // data error
              wbi_err_i;        // instruction error
 
input [7:0]   wbd_dat_i;        // ram data input
input [31:0]  wbi_dat_i;        // rom data input
 
output        wbd_we_o,         // data write enable
              wbd_stb_o,        // data strobe
              wbd_cyc_o,        // data cycle
              wbi_stb_o,        // instruction strobe
              wbi_cyc_o;        // instruction cycle
 
output [7:0]  wbd_dat_o;        // data output
 
output [15:0] wbd_adr_o,        // data address
              wbi_adr_o;        // instruction address
 
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0]  p0_i;             // port 0 input
output [7:0]  p0_o;             // port 0 output
`endif
 
`ifdef OC8051_PORT1
input  [7:0]  p1_i;             // port 1 input
output [7:0]  p1_o;             // port 1 output
`endif
 
`ifdef OC8051_PORT2
input  [7:0]  p2_i;             // port 2 input
output [7:0]  p2_o;             // port 2 output
`endif
 
`ifdef OC8051_PORT3
input  [7:0]  p3_i;             // port 3 input
output [7:0]  p3_o;             // port 3 output
`endif
 
`endif
 
 
 
 
 
 
`ifdef OC8051_UART
input         rxd_i;            // receive
output        txd_o;            // transnmit
`endif
 
`ifdef OC8051_TC01
input         t0_i,             // counter 0 input
              t1_i;             // counter 1 input
`endif
 
`ifdef OC8051_TC2
input         t2_i,             // counter 2 input
              t2ex_i;           //
`endif
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
wire    scanb_soi;
`endif
 
wire [7:0]  dptr_hi,
            dptr_lo,
            ri,
            data_out,
            op1,
            op2,
            op3,
            acc,
            p0_out,
            p1_out,
            p2_out,
            p3_out,
            sp,
            sp_w;
 
wire [31:0] idat_onchip;
 
wire [15:0] pc;
 
assign wbd_cyc_o = wbd_stb_o;
 
wire        src_sel3;
wire [1:0]  wr_sfr,
            src_sel2;
wire [2:0]  ram_rd_sel, // ram read
            ram_wr_sel, // ram write
            src_sel1;
 
wire [7:0]  ram_data,
            ram_out,    //data from ram
            sfr_out,
            wr_dat,
            wr_addr,    //ram write addres
            rd_addr;    //data ram read addres
wire        sfr_bit;
 
wire [1:0]  cy_sel,     //carry select; from decoder to cy_selct1
            bank_sel;
wire        rom_addr_sel,       //rom addres select; alu or pc
            rmw,
            ea_int;
 
wire        reti,
            intr,
            int_ack,
            istb;
wire [7:0]  int_src;
 
wire        mem_wait;
wire [2:0]  mem_act;
wire [3:0]  alu_op;     //alu operation (from decoder)
wire [1:0]  psw_set;    //write to psw or not; from decoder to psw (through register)
 
wire [7:0]  src1,       //alu sources 1
            src2,       //alu sources 2
            src3,       //alu sources 3
            des_acc,
            des1,       //alu destination 1
            des2;       //alu destinations 2
wire        desCy,      //carry out
            desAc,
            desOv,      //overflow
            alu_cy,
            wr,         //write to data ram
            wr_o;
 
wire        rd,         //read program rom
            pc_wr;
wire [2:0]  pc_wr_sel;  //program counter write select (from decoder to pc)
 
wire [7:0]  op1_n, //from memory_interface to decoder
            op2_n,
            op3_n;
 
wire [1:0]  comp_sel;   //select source1 and source2 to compare
wire        eq,         //result (from comp1 to decoder)
            srcAc,
            cy,
            rd_ind,
            wr_ind,
            comp_wait;
wire [2:0]  op1_cur;
 
wire        bit_addr,   //bit addresable instruction
            bit_data,   //bit data from ram to ram_select
            bit_out,    //bit data from ram_select to alu and cy_select
            bit_addr_o,
            wait_data;
 
//
// cpu to cache/wb_interface
wire        iack_i,
            istb_o,
            icyc_o;
wire [31:0] idat_i;
wire [15:0] iadr_o;
 
 
//
// decoder
oc8051_decoder oc8051_decoder1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .op_in              (op1_n              ),
          .op1_c              (op1_cur            ),
          .ram_rd_sel_o       (ram_rd_sel         ),
          .ram_wr_sel_o       (ram_wr_sel         ),
          .bit_addr           (bit_addr           ),
 
          .src_sel1           (src_sel1           ),
          .src_sel2           (src_sel2           ),
          .src_sel3           (src_sel3           ),
 
          .alu_op_o           (alu_op             ),
          .psw_set            (psw_set            ),
          .cy_sel             (cy_sel             ),
          .wr_o               (wr                 ),
          .pc_wr              (pc_wr              ),
          .pc_sel             (pc_wr_sel          ),
          .comp_sel           (comp_sel           ),
          .eq                 (eq                 ),
          .wr_sfr_o           (wr_sfr             ),
          .rd                 (rd                 ),
          .rmw                (rmw                ),
          .istb               (istb               ),
          .mem_act            (mem_act            ),
          .mem_wait           (mem_wait           ),
          .wait_data          (wait_data          )
     );
 
 
wire [7:0] sub_result;
//
//alu
oc8051_alu oc8051_alu1(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
          .op_code            (alu_op             ),
          .src1               (src1               ),
          .src2               (src2               ),
          .src3               (src3               ),
          .srcCy              (alu_cy             ),
          .srcAc              (srcAc              ),
          .des_acc            (des_acc            ),
          .sub_result         (sub_result         ),
          .des1               (des1               ),
          .des2               (des2               ),
          .desCy              (desCy              ),
          .desAc              (desAc              ),
          .desOv              (desOv              ),
          .bit_in(bit_out)
       );
 
//
//data ram
oc8051_ram_top oc8051_ram_top1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .rd_addr            (rd_addr            ),
          .rd_data            (ram_data           ),
          .wr_addr            (wr_addr            ),
          .bit_addr           (bit_addr_o         ),
          .wr_data            (wr_dat             ),
          .wr                 (wr_o &&
                               (!wr_addr[7] || wr_ind)),
          .bit_data_in        (desCy              ),
          .bit_data_out       (bit_data           )
`ifdef OC8051_BIST
         ,
          .scanb_rst          (scanb_rst          ),
          .scanb_clk          (scanb_clk          ),
          .scanb_si           (scanb_soi          ),
          .scanb_so           (scanb_so           ),
          .scanb_en           (scanb_en           )
`endif
                               );
 
//
 
oc8051_alu_src_sel oc8051_alu_src_sel1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .rd                 (rd                 ),
 
          .sel1               (src_sel1           ),
          .sel2               (src_sel2           ),
          .sel3               (src_sel3           ),
 
          .acc                (acc                ),
          .ram                (ram_out            ),
          .pc                 (pc                 ),
          .dptr               ({dptr_hi, dptr_lo} ),
          .op1                (op1_n              ),
          .op2                (op2_n              ),
          .op3                (op3_n              ),
 
          .src1               (src1               ),
          .src2               (src2               ),
          .src3               (src3               )
      );
 
 
//
//
oc8051_comp oc8051_comp1(
          .sel                (comp_sel           ),
          .eq                 (eq                 ),
          .b_in               (bit_out            ),
          .cy                 (cy                 ),
          .acc                (acc                ),
          .des                (sub_result         )
    );
 
 
//
//program rom
`ifdef OC8051_ROM
  oc8051_rom oc8051_rom1(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
          .ea_int             (ea_int             ),
          .addr               (iadr_o             ),
          .data_o             (idat_onchip        )
     );
`else
  assign ea_int = 1'b0;
  assign idat_onchip = 32'h0;
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      $display("\t * ");
      $display("\t * Internal rom disabled!!!");
      $display("\t * ");
    end
 
  `endif
 
`endif
 
//
//
oc8051_cy_select oc8051_cy_select1(
          .cy_sel             (cy_sel             ),
          .cy_in              (cy                 ),
          .data_in            (bit_out            ),
          .data_out           (alu_cy             )
    );
//
//
oc8051_indi_addr oc8051_indi_addr1 (
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
          .wr_addr            (wr_addr            ),
          .data_in            (wr_dat             ),
          .wr                 (wr_o               ),
          .wr_bit             (bit_addr_o         ),
          .ri_out             (ri                 ),
          .sel                (op1_cur[0]         ),
          .bank               (bank_sel           )
 );
 
 
 
assign icyc_o = istb_o;
//
//
oc8051_memory_interface oc8051_memory_interface1(
          .clk                (wb_clk_i           ),
          .rst                (wb_rst_i           ),
// internal ram
          .wr_i               (wr                 ),
          .wr_o               (wr_o               ),
          .wr_bit_i           (bit_addr           ),
          .wr_bit_o           (bit_addr_o         ),
          .wr_dat             (wr_dat             ),
          .des_acc            (des_acc            ),
          .des1               (des1               ),
          .des2               (des2               ),
          .rd_addr            (rd_addr            ),
          .wr_addr            (wr_addr            ),
          .wr_ind             (wr_ind             ),
          .bit_in             (bit_data           ),
          .in_ram             (ram_data           ),
          .sfr                (sfr_out            ),
          .sfr_bit            (sfr_bit            ),
          .bit_out            (bit_out            ),
          .iram_out           (ram_out            ),
 
// external instrauction rom
          .iack_i             (iack_i             ),
          .iadr_o             (iadr_o             ),
          .idat_i             (idat_i             ),
          .istb_o             (istb_o             ),
 
// internal instruction rom
          .idat_onchip        (idat_onchip        ),
 
// data memory
          .dadr_o             (wbd_adr_o          ),
          .ddat_o             (wbd_dat_o          ),
          .dwe_o              (wbd_we_o           ),
          .dstb_o             (wbd_stb_o          ),
          .ddat_i             (wbd_dat_i          ),
          .dack_i             (wbd_ack_i          ),
 
// from decoder
          .rd_sel             (ram_rd_sel         ),
          .wr_sel             (ram_wr_sel         ),
          .rn                 ({bank_sel, op1_cur}),
          .rd_ind             (rd_ind             ),
          .rd                 (rd                 ),
          .mem_act            (mem_act            ),
          .mem_wait           (mem_wait           ),
 
// external access
          .ea                 (ea_in              ),
          .ea_int             (ea_int             ),
 
// instructions outputs to cpu
          .op1_out            (op1_n              ),
          .op2_out            (op2_n              ),
          .op3_out            (op3_n              ),
 
// interrupt interface
          .intr               (intr               ),
                       .int_v(int_src),
          .int_ack            (int_ack            ),
          .istb               (istb               ),
          .reti               (reti               ),
 
//pc
          .pc_wr_sel          (pc_wr_sel          ),
          .pc_wr              (pc_wr & comp_wait  ),
          .pc                 (pc                 ),
 
// sfr's
          .sp_w               (sp_w               ),
          .dptr               ({dptr_hi, dptr_lo} ),
          .ri                 (ri                 ),
          .acc                (acc                ),
          .sp                 (sp                 )
       );
 
 
//
//
 
oc8051_sfr oc8051_sfr1(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
          .adr0               (rd_addr[7:0]       ),
          .adr1               (wr_addr[7:0]       ),
          .dat0               (sfr_out            ),
          .dat1               (wr_dat             ),
          .dat2               (des2               ),
          .des_acc            (des_acc            ),
          .we                 (wr_o && !wr_ind    ),
          .bit_in             (desCy              ),
          .bit_out            (sfr_bit            ),
          .wr_bit             (bit_addr_o         ),
          .ram_rd_sel         (ram_rd_sel         ),
          .ram_wr_sel         (ram_wr_sel         ),
          .wr_sfr             (wr_sfr             ),
          .comp_sel           (comp_sel           ),
          .comp_wait          (comp_wait          ),
// acc
          .acc                (acc                ),
// sp
          .sp                 (sp                 ),
          .sp_w               (sp_w               ),
// psw
          .bank_sel           (bank_sel           ),
          .desAc              (desAc              ),
          .desOv              (desOv              ),
          .psw_set            (psw_set            ),
          .srcAc              (srcAc              ),
          .cy                 (cy                 ),
// ports
          .rmw                (rmw                ),
 
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_out             (p0_o               ),
          .p0_in              (p0_i               ),
        `endif
 
        `ifdef OC8051_PORT1
          .p1_out             (p1_o               ),
          .p1_in              (p1_i               ),
        `endif
 
        `ifdef OC8051_PORT2
          .p2_out             (p2_o               ),
          .p2_in              (p2_i               ),
        `endif
 
        `ifdef OC8051_PORT3
          .p3_out             (p3_o               ),
          .p3_in              (p3_i               ),
        `endif
  `endif
 
// uart
        `ifdef OC8051_UART
          .rxd                (rxd_i              ),
          .txd                (txd_o              ),
        `endif
 
// int
          .int_ack            (int_ack            ),
          .intr               (intr               ),
          .int0               (int0_i             ),
          .int1               (int1_i             ),
          .reti               (reti               ),
          .int_src            (int_src            ),
 
// t/c 0,1
        `ifdef OC8051_TC01
          .t0                 (t0_i               ),
          .t1                 (t1_i               ),
        `endif
 
// t/c 2
        `ifdef OC8051_TC2
          .t2                 (t2_i               ),
          .t2ex               (t2ex_i             ),
        `endif
 
// dptr
          .dptr_hi            (dptr_hi            ),
          .dptr_lo            (dptr_lo            ),
          .wait_data          (wait_data          )
       );
 
 
 
 
 
 
 
 
 
 
  `ifdef OC8051_BIST
       assign scanb_soi=scanb_si;
  `endif
 
  `ifdef OC8051_WB
 
    oc8051_wb_iinterface oc8051_wb_iinterface(
          .rst                (wb_rst_i           ),
          .clk                (wb_clk_i           ),
    // cpu
          .adr_i              (iadr_o             ),
          .dat_o              (idat_i             ),
          .stb_i              (istb_o             ),
          .ack_o              (iack_i             ),
          .cyc_i              (icyc_o             ),
    // external rom
          .dat_i              (wbi_dat_i          ),
          .stb_o              (wbi_stb_o          ),
          .adr_o              (wbi_adr_o          ),
          .ack_i              (wbi_ack_i          ),
          .cyc_o              (wbi_cyc_o          )
       );
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      #1
      $display("\t * ");
      $display("\t * External rom interface: WB interface");
      $display("\t * ");
    end
 
  `endif
 
  `else
 
    assign wbi_adr_o = iadr_o    ;
    assign idat_i    = wbi_dat_i ;
    assign wbi_stb_o = 1'b1      ;
    assign iack_i    = wbi_ack_i ;
    assign wbi_cyc_o = 1'b1      ;
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      #1
      $display("\t * ");
      $display("\t * External rom interface: Pipelined interface");
      $display("\t * ");
    end
 
  `endif
 
 
  `endif
 
 
 
// synopsys translate_off
// Debug Purpose only
// Stack Pointer Push & Pop analysis
reg [7:0]   StackMem[$];
reg  [7:0]  stack_pop;
reg  [7:0]  pushpop_cnt;
 
// Assumption, Both Write and Read access will not be
// possbile in single clock cycle
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
   if(wb_rst_i) begin
      pushpop_cnt = 0;
   end
   else begin
      if(ram_wr_sel==`OC8051_RWS_SP) begin
            StackMem.push_back(wr_dat);
            pushpop_cnt = pushpop_cnt + 1;
      end
      if(ram_rd_sel==`OC8051_RRS_SP) begin
            stack_pop = StackMem.pop_back();
            pushpop_cnt = pushpop_cnt - 1;
            #2  // Add 1ns Delay to take care of Ram Dealy
            if(stack_pop != ram_data) begin
              $display("ERROR: Invalid Stack Pointer Pop Detected, Exp: %x,Rxd:%x",stack_pop,ram_data);
              $stop;
            end
      end
   end
end
 
// synopsys translate_on
 
endmodule

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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Blame information for rev 78

Line No.	Rev	Author	Line
1	68	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6	76	dinesha	`//// http://www.opencores.org/cores/turbo8051/ ////`
7	68	dinesha	`//// ////`
8			`//// Description ////`
9			`//// 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16	76	dinesha	`//// - Dinesh Annayya, dinesha@opencores.org ////`
17	68	dinesha	`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.32 2003/06/20 13:36:37 simont`
49			`// ram modules added.`
50			`//`
51			`// Revision 1.31 2003/06/17 14:17:22 simont`
52			`// BIST signals added.`
53			`//`
54			`// Revision 1.30 2003/06/03 16:51:24 simont`
55			`// include "8051_defines" added.`
56			`//`
57			`// Revision 1.29 2003/05/07 12:36:03 simont`
58			`// chsnge comp.des to des1`
59			`//`
60			`// Revision 1.28 2003/05/06 09:41:35 simont`
61			`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
62			`//`
63			`// Revision 1.27 2003/05/05 15:46:37 simont`
64			`// add aditional alu destination to solve critical path.`
65			`//`
66			`// Revision 1.26 2003/04/29 11:24:31 simont`
67			`// fix bug in case execution of two data dependent instructions.`
68			`//`
69			`// Revision 1.25 2003/04/25 17:15:51 simont`
70			`// change branch instruction execution (reduse needed clock periods).`
71			`//`
72			`// Revision 1.24 2003/04/11 10:05:59 simont`
73			`// deifne OC8051_ROM added`
74			`//`
75			`// Revision 1.23 2003/04/10 12:43:19 simont`
76			`// defines for pherypherals added`
77			`//`
78			`// Revision 1.22 2003/04/09 16:24:04 simont`
79			`// change wr_sft to 2 bit wire.`
80			`//`
81			`// Revision 1.21 2003/04/09 15:49:42 simont`
82			`// Register oc8051_sfr dato output, add signal wait_data.`
83			`//`
84			`// Revision 1.20 2003/04/03 19:13:28 simont`
85			`// Include instruction cache.`
86			`//`
87			`// Revision 1.19 2003/04/02 15:08:30 simont`
88			`// raname signals.`
89			`//`
90			`// Revision 1.18 2003/01/13 14:14:41 simont`
91			`// replace some modules`
92			`//`
93			`// Revision 1.17 2002/11/05 17:23:54 simont`
94			`// add module oc8051_sfr, 256 bytes internal ram`
95			`//`
96			`// Revision 1.16 2002/10/28 14:55:00 simont`
97			`// fix bug in interface to external data ram`
98			`//`
99			`// Revision 1.15 2002/10/23 16:53:39 simont`
100			`// fix bugs in instruction interface`
101			`//`
102			`// Revision 1.14 2002/10/17 18:50:00 simont`
103			`// cahnge interface to instruction rom`
104			`//`
105			`// Revision 1.13 2002/09/30 17:33:59 simont`
106			`// prepared header`
107			`//`
108			`//`
109
110
111	76	dinesha	`include "top_defines.v"
112	68	dinesha
113			`module oc8051_top (wb_rst_i, wb_clk_i,`
114			`//interface to instruction rom`
115			`wbi_adr_o,`
116			`wbi_dat_i,`
117			`wbi_stb_o,`
118			`wbi_ack_i,`
119			`wbi_cyc_o,`
120			`wbi_err_i,`
121
122			`//interface to data ram`
123			`wbd_dat_i,`
124			`wbd_dat_o,`
125			`wbd_adr_o,`
126			`wbd_we_o,`
127			`wbd_ack_i,`
128			`wbd_stb_o,`
129			`wbd_cyc_o,`
130			`wbd_err_i,`
131
132			`// interrupt interface`
133			`int0_i,`
134			`int1_i,`
135
136
137			`// port interface`
138			`ifdef OC8051_PORTS
139			`ifdef OC8051_PORT0
140			`p0_i,`
141			`p0_o,`
142			`endif
143
144			`ifdef OC8051_PORT1
145			`p1_i,`
146			`p1_o,`
147			`endif
148
149			`ifdef OC8051_PORT2
150			`p2_i,`
151			`p2_o,`
152			`endif
153
154			`ifdef OC8051_PORT3
155			`p3_i,`
156			`p3_o,`
157			`endif
158			`endif
159
160			`// serial interface`
161			`ifdef OC8051_UART
162			`rxd_i, txd_o,`
163			`endif
164
165			`// counter interface`
166			`ifdef OC8051_TC01
167			`t0_i, t1_i,`
168			`endif
169
170			`ifdef OC8051_TC2
171			`t2_i, t2ex_i,`
172			`endif
173
174			`// BIST`
175			`ifdef OC8051_BIST
176			`scanb_rst,`
177			`scanb_clk,`
178			`scanb_si,`
179			`scanb_so,`
180			`scanb_en,`
181			`endif
182			`// external access (active low)`
183			`ea_in`
184			`);`
185
186
187
188			`input wb_rst_i, // reset input`
189			`wb_clk_i, // clock input`
190			`int0_i, // interrupt 0`
191			`int1_i, // interrupt 1`
192			`ea_in, // external access`
193			`wbd_ack_i, // data acknowalge`
194			`wbi_ack_i, // instruction acknowlage`
195			`wbd_err_i, // data error`
196			`wbi_err_i; // instruction error`
197
198			`input [7:0] wbd_dat_i; // ram data input`
199			`input [31:0] wbi_dat_i; // rom data input`
200
201			`output wbd_we_o, // data write enable`
202			`wbd_stb_o, // data strobe`
203			`wbd_cyc_o, // data cycle`
204			`wbi_stb_o, // instruction strobe`
205			`wbi_cyc_o; // instruction cycle`
206
207			`output [7:0] wbd_dat_o; // data output`
208
209			`output [15:0] wbd_adr_o, // data address`
210			`wbi_adr_o; // instruction address`
211
212			`ifdef OC8051_PORTS
213
214			`ifdef OC8051_PORT0
215			`input [7:0] p0_i; // port 0 input`
216			`output [7:0] p0_o; // port 0 output`
217			`endif
218
219			`ifdef OC8051_PORT1
220			`input [7:0] p1_i; // port 1 input`
221			`output [7:0] p1_o; // port 1 output`
222			`endif
223
224			`ifdef OC8051_PORT2
225			`input [7:0] p2_i; // port 2 input`
226			`output [7:0] p2_o; // port 2 output`
227			`endif
228
229			`ifdef OC8051_PORT3
230			`input [7:0] p3_i; // port 3 input`
231			`output [7:0] p3_o; // port 3 output`
232			`endif
233
234			`endif
235
236
237
238
239
240
241			`ifdef OC8051_UART
242			`input rxd_i; // receive`
243			`output txd_o; // transnmit`
244			`endif
245
246			`ifdef OC8051_TC01
247			`input t0_i, // counter 0 input`
248			`t1_i; // counter 1 input`
249			`endif
250
251			`ifdef OC8051_TC2
252			`input t2_i, // counter 2 input`
253			`t2ex_i; //`
254			`endif
255
256			`ifdef OC8051_BIST
257			`input scanb_rst;`
258			`input scanb_clk;`
259			`input scanb_si;`
260			`output scanb_so;`
261			`input scanb_en;`
262			`wire scanb_soi;`
263			`endif
264
265			`wire [7:0] dptr_hi,`
266			`dptr_lo,`
267			`ri,`
268			`data_out,`
269			`op1,`
270			`op2,`
271			`op3,`
272			`acc,`
273			`p0_out,`
274			`p1_out,`
275			`p2_out,`
276			`p3_out,`
277			`sp,`
278			`sp_w;`
279
280			`wire [31:0] idat_onchip;`
281
282			`wire [15:0] pc;`
283
284			`assign wbd_cyc_o = wbd_stb_o;`
285
286			`wire src_sel3;`
287			`wire [1:0] wr_sfr,`
288			`src_sel2;`
289			`wire [2:0] ram_rd_sel, // ram read`
290			`ram_wr_sel, // ram write`
291			`src_sel1;`
292
293			`wire [7:0] ram_data,`
294			`ram_out, //data from ram`
295			`sfr_out,`
296			`wr_dat,`
297			`wr_addr, //ram write addres`
298			`rd_addr; //data ram read addres`
299			`wire sfr_bit;`
300
301			`wire [1:0] cy_sel, //carry select; from decoder to cy_selct1`
302			`bank_sel;`
303			`wire rom_addr_sel, //rom addres select; alu or pc`
304			`rmw,`
305			`ea_int;`
306
307			`wire reti,`
308			`intr,`
309			`int_ack,`
310			`istb;`
311			`wire [7:0] int_src;`
312
313			`wire mem_wait;`
314			`wire [2:0] mem_act;`
315			`wire [3:0] alu_op; //alu operation (from decoder)`
316			`wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)`
317
318			`wire [7:0] src1, //alu sources 1`
319			`src2, //alu sources 2`
320			`src3, //alu sources 3`
321			`des_acc,`
322			`des1, //alu destination 1`
323			`des2; //alu destinations 2`
324			`wire desCy, //carry out`
325			`desAc,`
326			`desOv, //overflow`
327			`alu_cy,`
328			`wr, //write to data ram`
329			`wr_o;`
330
331			`wire rd, //read program rom`
332			`pc_wr;`
333			`wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)`
334
335			`wire [7:0] op1_n, //from memory_interface to decoder`
336			`op2_n,`
337			`op3_n;`
338
339			`wire [1:0] comp_sel; //select source1 and source2 to compare`
340			`wire eq, //result (from comp1 to decoder)`
341			`srcAc,`
342			`cy,`
343			`rd_ind,`
344			`wr_ind,`
345			`comp_wait;`
346			`wire [2:0] op1_cur;`
347
348			`wire bit_addr, //bit addresable instruction`
349			`bit_data, //bit data from ram to ram_select`
350			`bit_out, //bit data from ram_select to alu and cy_select`
351			`bit_addr_o,`
352			`wait_data;`
353
354			`//`
355			`// cpu to cache/wb_interface`
356			`wire iack_i,`
357			`istb_o,`
358			`icyc_o;`
359			`wire [31:0] idat_i;`
360			`wire [15:0] iadr_o;`
361
362
363			`//`
364			`// decoder`
365			`oc8051_decoder oc8051_decoder1(`
366			`.clk (wb_clk_i ),`
367			`.rst (wb_rst_i ),`
368			`.op_in (op1_n ),`
369			`.op1_c (op1_cur ),`
370			`.ram_rd_sel_o (ram_rd_sel ),`
371			`.ram_wr_sel_o (ram_wr_sel ),`
372			`.bit_addr (bit_addr ),`
373
374			`.src_sel1 (src_sel1 ),`
375			`.src_sel2 (src_sel2 ),`
376			`.src_sel3 (src_sel3 ),`
377
378			`.alu_op_o (alu_op ),`
379			`.psw_set (psw_set ),`
380			`.cy_sel (cy_sel ),`
381			`.wr_o (wr ),`
382			`.pc_wr (pc_wr ),`
383			`.pc_sel (pc_wr_sel ),`
384			`.comp_sel (comp_sel ),`
385			`.eq (eq ),`
386			`.wr_sfr_o (wr_sfr ),`
387			`.rd (rd ),`
388			`.rmw (rmw ),`
389			`.istb (istb ),`
390			`.mem_act (mem_act ),`
391			`.mem_wait (mem_wait ),`
392			`.wait_data (wait_data )`
393			`);`
394
395
396			`wire [7:0] sub_result;`
397			`//`
398			`//alu`
399			`oc8051_alu oc8051_alu1(`
400			`.rst (wb_rst_i ),`
401			`.clk (wb_clk_i ),`
402			`.op_code (alu_op ),`
403			`.src1 (src1 ),`
404			`.src2 (src2 ),`
405			`.src3 (src3 ),`
406			`.srcCy (alu_cy ),`
407			`.srcAc (srcAc ),`
408			`.des_acc (des_acc ),`
409			`.sub_result (sub_result ),`
410			`.des1 (des1 ),`
411			`.des2 (des2 ),`
412			`.desCy (desCy ),`
413			`.desAc (desAc ),`
414			`.desOv (desOv ),`
415			`.bit_in(bit_out)`
416			`);`
417
418			`//`
419			`//data ram`
420			`oc8051_ram_top oc8051_ram_top1(`
421			`.clk (wb_clk_i ),`
422			`.rst (wb_rst_i ),`
423			`.rd_addr (rd_addr ),`
424			`.rd_data (ram_data ),`
425			`.wr_addr (wr_addr ),`
426			`.bit_addr (bit_addr_o ),`
427			`.wr_data (wr_dat ),`
428			`.wr (wr_o &&`
429			`(!wr_addr[7] \|\| wr_ind)),`
430			`.bit_data_in (desCy ),`
431			`.bit_data_out (bit_data )`
432			`ifdef OC8051_BIST
433			`,`
434			`.scanb_rst (scanb_rst ),`
435			`.scanb_clk (scanb_clk ),`
436			`.scanb_si (scanb_soi ),`
437			`.scanb_so (scanb_so ),`
438			`.scanb_en (scanb_en )`
439			`endif
440			`);`
441
442			`//`
443
444			`oc8051_alu_src_sel oc8051_alu_src_sel1(`
445			`.clk (wb_clk_i ),`
446			`.rst (wb_rst_i ),`
447			`.rd (rd ),`
448
449			`.sel1 (src_sel1 ),`
450			`.sel2 (src_sel2 ),`
451			`.sel3 (src_sel3 ),`
452
453			`.acc (acc ),`
454			`.ram (ram_out ),`
455			`.pc (pc ),`
456			`.dptr ({dptr_hi, dptr_lo} ),`
457			`.op1 (op1_n ),`
458			`.op2 (op2_n ),`
459			`.op3 (op3_n ),`
460
461			`.src1 (src1 ),`
462			`.src2 (src2 ),`
463			`.src3 (src3 )`
464			`);`
465
466
467			`//`
468			`//`
469			`oc8051_comp oc8051_comp1(`
470			`.sel (comp_sel ),`
471			`.eq (eq ),`
472			`.b_in (bit_out ),`
473			`.cy (cy ),`
474			`.acc (acc ),`
475			`.des (sub_result )`
476			`);`
477
478
479			`//`
480			`//program rom`
481			`ifdef OC8051_ROM
482			`oc8051_rom oc8051_rom1(`
483			`.rst (wb_rst_i ),`
484			`.clk (wb_clk_i ),`
485			`.ea_int (ea_int ),`
486			`.addr (iadr_o ),`
487			`.data_o (idat_onchip )`
488			`);`
489			`else
490			`assign ea_int = 1'b0;`
491			`assign idat_onchip = 32'h0;`
492
493			`ifdef OC8051_SIMULATION
494
495			`initial`
496			`begin`
497			`$display("\t * ");`
498			`$display("\t * Internal rom disabled!!!");`
499			`$display("\t * ");`
500			`end`
501
502			`endif
503
504			`endif
505
506			`//`
507			`//`
508			`oc8051_cy_select oc8051_cy_select1(`
509			`.cy_sel (cy_sel ),`
510			`.cy_in (cy ),`
511			`.data_in (bit_out ),`
512			`.data_out (alu_cy )`
513			`);`
514			`//`
515			`//`
516			`oc8051_indi_addr oc8051_indi_addr1 (`
517			`.clk (wb_clk_i ),`
518			`.rst (wb_rst_i ),`
519			`.wr_addr (wr_addr ),`
520			`.data_in (wr_dat ),`
521			`.wr (wr_o ),`
522			`.wr_bit (bit_addr_o ),`
523			`.ri_out (ri ),`
524			`.sel (op1_cur[0] ),`
525			`.bank (bank_sel )`
526			`);`
527
528
529
530			`assign icyc_o = istb_o;`
531			`//`
532			`//`
533			`oc8051_memory_interface oc8051_memory_interface1(`
534			`.clk (wb_clk_i ),`
535			`.rst (wb_rst_i ),`
536			`// internal ram`
537			`.wr_i (wr ),`
538			`.wr_o (wr_o ),`
539			`.wr_bit_i (bit_addr ),`
540			`.wr_bit_o (bit_addr_o ),`
541			`.wr_dat (wr_dat ),`
542			`.des_acc (des_acc ),`
543			`.des1 (des1 ),`
544			`.des2 (des2 ),`
545			`.rd_addr (rd_addr ),`
546			`.wr_addr (wr_addr ),`
547			`.wr_ind (wr_ind ),`
548			`.bit_in (bit_data ),`
549			`.in_ram (ram_data ),`
550			`.sfr (sfr_out ),`
551			`.sfr_bit (sfr_bit ),`
552			`.bit_out (bit_out ),`
553			`.iram_out (ram_out ),`
554
555			`// external instrauction rom`
556			`.iack_i (iack_i ),`
557			`.iadr_o (iadr_o ),`
558			`.idat_i (idat_i ),`
559			`.istb_o (istb_o ),`
560
561			`// internal instruction rom`
562			`.idat_onchip (idat_onchip ),`
563
564			`// data memory`
565			`.dadr_o (wbd_adr_o ),`
566			`.ddat_o (wbd_dat_o ),`
567			`.dwe_o (wbd_we_o ),`
568			`.dstb_o (wbd_stb_o ),`
569			`.ddat_i (wbd_dat_i ),`
570			`.dack_i (wbd_ack_i ),`
571
572			`// from decoder`
573			`.rd_sel (ram_rd_sel ),`
574			`.wr_sel (ram_wr_sel ),`
575			`.rn ({bank_sel, op1_cur}),`
576			`.rd_ind (rd_ind ),`
577			`.rd (rd ),`
578			`.mem_act (mem_act ),`
579			`.mem_wait (mem_wait ),`
580
581			`// external access`
582			`.ea (ea_in ),`
583			`.ea_int (ea_int ),`
584
585			`// instructions outputs to cpu`
586			`.op1_out (op1_n ),`
587			`.op2_out (op2_n ),`
588			`.op3_out (op3_n ),`
589
590			`// interrupt interface`
591			`.intr (intr ),`
592			`.int_v(int_src),`
593			`.int_ack (int_ack ),`
594			`.istb (istb ),`
595			`.reti (reti ),`
596
597			`//pc`
598			`.pc_wr_sel (pc_wr_sel ),`
599			`.pc_wr (pc_wr & comp_wait ),`
600			`.pc (pc ),`
601
602			`// sfr's`
603			`.sp_w (sp_w ),`
604			`.dptr ({dptr_hi, dptr_lo} ),`
605			`.ri (ri ),`
606			`.acc (acc ),`
607			`.sp (sp )`
608			`);`
609
610
611			`//`
612			`//`
613
614			`oc8051_sfr oc8051_sfr1(`
615			`.rst (wb_rst_i ),`
616			`.clk (wb_clk_i ),`
617			`.adr0 (rd_addr[7:0] ),`
618			`.adr1 (wr_addr[7:0] ),`
619			`.dat0 (sfr_out ),`
620			`.dat1 (wr_dat ),`
621			`.dat2 (des2 ),`
622			`.des_acc (des_acc ),`
623			`.we (wr_o && !wr_ind ),`
624			`.bit_in (desCy ),`
625			`.bit_out (sfr_bit ),`
626			`.wr_bit (bit_addr_o ),`
627			`.ram_rd_sel (ram_rd_sel ),`
628			`.ram_wr_sel (ram_wr_sel ),`
629			`.wr_sfr (wr_sfr ),`
630			`.comp_sel (comp_sel ),`
631			`.comp_wait (comp_wait ),`
632			`// acc`
633			`.acc (acc ),`
634			`// sp`
635			`.sp (sp ),`
636			`.sp_w (sp_w ),`
637			`// psw`
638			`.bank_sel (bank_sel ),`
639			`.desAc (desAc ),`
640			`.desOv (desOv ),`
641			`.psw_set (psw_set ),`
642			`.srcAc (srcAc ),`
643			`.cy (cy ),`
644			`// ports`
645			`.rmw (rmw ),`
646
647			`ifdef OC8051_PORTS
648			`ifdef OC8051_PORT0
649			`.p0_out (p0_o ),`
650			`.p0_in (p0_i ),`
651			`endif
652
653			`ifdef OC8051_PORT1
654			`.p1_out (p1_o ),`
655			`.p1_in (p1_i ),`
656			`endif
657
658			`ifdef OC8051_PORT2
659			`.p2_out (p2_o ),`
660			`.p2_in (p2_i ),`
661			`endif
662
663			`ifdef OC8051_PORT3
664			`.p3_out (p3_o ),`
665			`.p3_in (p3_i ),`
666			`endif
667			`endif
668
669			`// uart`
670			`ifdef OC8051_UART
671			`.rxd (rxd_i ),`
672			`.txd (txd_o ),`
673			`endif
674
675			`// int`
676			`.int_ack (int_ack ),`
677			`.intr (intr ),`
678			`.int0 (int0_i ),`
679			`.int1 (int1_i ),`
680			`.reti (reti ),`
681			`.int_src (int_src ),`
682
683			`// t/c 0,1`
684			`ifdef OC8051_TC01
685			`.t0 (t0_i ),`
686			`.t1 (t1_i ),`
687			`endif
688
689			`// t/c 2`
690			`ifdef OC8051_TC2
691			`.t2 (t2_i ),`
692			`.t2ex (t2ex_i ),`
693			`endif
694
695			`// dptr`
696			`.dptr_hi (dptr_hi ),`
697			`.dptr_lo (dptr_lo ),`
698			`.wait_data (wait_data )`
699			`);`
700
701
702
703
704
705
706
707
708
709
710			`ifdef OC8051_BIST
711			`assign scanb_soi=scanb_si;`
712			`endif
713
714			`ifdef OC8051_WB
715
716			`oc8051_wb_iinterface oc8051_wb_iinterface(`
717			`.rst (wb_rst_i ),`
718			`.clk (wb_clk_i ),`
719			`// cpu`
720			`.adr_i (iadr_o ),`
721			`.dat_o (idat_i ),`
722			`.stb_i (istb_o ),`
723			`.ack_o (iack_i ),`
724			`.cyc_i (icyc_o ),`
725			`// external rom`
726			`.dat_i (wbi_dat_i ),`
727			`.stb_o (wbi_stb_o ),`
728			`.adr_o (wbi_adr_o ),`
729			`.ack_i (wbi_ack_i ),`
730			`.cyc_o (wbi_cyc_o )`
731			`);`
732
733			`ifdef OC8051_SIMULATION
734
735			`initial`
736			`begin`
737			`#1`
738			`$display("\t * ");`
739			`$display("\t * External rom interface: WB interface");`
740			`$display("\t * ");`
741			`end`
742
743			`endif
744
745			`else
746
747			`assign wbi_adr_o = iadr_o ;`
748			`assign idat_i = wbi_dat_i ;`
749			`assign wbi_stb_o = 1'b1 ;`
750			`assign iack_i = wbi_ack_i ;`
751			`assign wbi_cyc_o = 1'b1 ;`
752
753			`ifdef OC8051_SIMULATION
754
755			`initial`
756			`begin`
757			`#1`
758			`$display("\t * ");`
759			`$display("\t * External rom interface: Pipelined interface");`
760			`$display("\t * ");`
761			`end`
762
763			`endif
764
765
766			`endif
767
768
769
770			`// synopsys translate_off`
771			`// Debug Purpose only`
772			`// Stack Pointer Push & Pop analysis`
773			`reg [7:0] StackMem[$];`
774			`reg [7:0] stack_pop;`
775			`reg [7:0] pushpop_cnt;`
776
777			`// Assumption, Both Write and Read access will not be`
778			`// possbile in single clock cycle`
779			`always @(posedge wb_clk_i or posedge wb_rst_i)`
780			`begin`
781			`if(wb_rst_i) begin`
782			`pushpop_cnt = 0;`
783			`end`
784			`else begin`
785			if(ram_wr_sel==`OC8051_RWS_SP) begin
786			`StackMem.push_back(wr_dat);`
787			`pushpop_cnt = pushpop_cnt + 1;`
788			`end`
789			if(ram_rd_sel==`OC8051_RRS_SP) begin
790			`stack_pop = StackMem.pop_back();`
791			`pushpop_cnt = pushpop_cnt - 1;`
792			`#2 // Add 1ns Delay to take care of Ram Dealy`
793			`if(stack_pop != ram_data) begin`
794			`$display("ERROR: Invalid Stack Pointer Pop Detected, Exp: %x,Rxd:%x",stack_pop,ram_data);`
795			`$stop;`
796			`end`
797			`end`
798			`end`
799			`end`
800
801			`// synopsys translate_on`
802
803	76	dinesha	`endmodule`