OpenCores
URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [rtl/] [clkgen/] [clkgen.v] - Blame information for rev 76

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 dinesha
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Tubo 8051 cores clockgen Module                             ////
4
////                                                              ////
5
////  This file is part of the Turbo 8051 cores project           ////
6
////  http://www.opencores.org/cores/turbo8051/                   ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Turbo 8051 definitions.                                     ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////    nothing                                                   ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Dinesh Annayya, dinesha@opencores.org                 ////
16
////                                                              ////
17 76 dinesha
////  Revision : Mar 2, 2011                                      //// 
18
////                                                              ////
19 8 dinesha
//////////////////////////////////////////////////////////////////////
20
////                                                              ////
21
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
22
////                                                              ////
23
//// This source file may be used and distributed without         ////
24
//// restriction provided that this copyright statement is not    ////
25
//// removed from the file and that any derivative work contains  ////
26
//// the original copyright notice and the associated disclaimer. ////
27
////                                                              ////
28
//// This source file is free software; you can redistribute it   ////
29
//// and/or modify it under the terms of the GNU Lesser General   ////
30
//// Public License as published by the Free Software Foundation; ////
31
//// either version 2.1 of the License, or (at your option) any   ////
32
//// later version.                                               ////
33
////                                                              ////
34
//// This source is distributed in the hope that it will be       ////
35
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
36
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
37
//// PURPOSE.  See the GNU Lesser General Public License for more ////
38
//// details.                                                     ////
39
////                                                              ////
40
//// You should have received a copy of the GNU Lesser General    ////
41
//// Public License along with this source; if not, download it   ////
42
//// from http://www.opencores.org/lgpl.shtml                     ////
43
////                                                              ////
44
//////////////////////////////////////////////////////////////////////
45
 
46
module clkgen (
47
               reset_n      ,
48
               fastsim_mode ,
49 25 dinesha
               mastermode   ,
50 8 dinesha
               xtal_clk     ,
51
               clkout       ,
52
               gen_resetn   ,
53 25 dinesha
               risc_reset   ,
54 8 dinesha
               app_clk      ,
55
               uart_ref_clk
56
              );
57
 
58
 
59
 
60
input           reset_n        ; // Async reset signal
61
input         fastsim_mode   ; // fast sim mode = 1
62 25 dinesha
input         mastermode     ; // 1 : Risc master mode
63 8 dinesha
input           xtal_clk       ; // Xtal clock-25Mhx 
64
output        clkout         ; // clock output, 250Mhz
65
output        gen_resetn     ; // internally generated reset
66 25 dinesha
output        risc_reset      ; // internally generated reset
67 8 dinesha
output        app_clk        ; // application clock
68
output        uart_ref_clk   ; // uart 16x Ref clock
69
 
70
 
71
wire          hard_reset_st  ;
72
wire          configure_st   ;
73
wire          wait_pll_st    ;
74
wire          run_st         ;
75 25 dinesha
wire          slave_run_st   ;
76 8 dinesha
reg           pll_done       ;
77
reg [11:0]         pll_count      ;
78 25 dinesha
reg [2:0]          clkgen_ps      ;
79 8 dinesha
reg           gen_resetn     ; // internally generated reset
80 25 dinesha
reg           risc_reset      ; // internally generated reset
81 8 dinesha
 
82
 
83
assign        clkout = app_clk;
84
wire          pllout;
85
/***********************************************
86
 Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
87
*********************************************************/
88 57 dinesha
/*******************
89 8 dinesha
altera_stargate_pll u_pll (
90
        . areset     (!reset_n ),
91
        . inclk0     (xtal_clk),
92
        . c0         (pllout),
93
        . locked     ()
94
       );
95 57 dinesha
*************************/
96 8 dinesha
 
97 57 dinesha
assign pllout = xtal_clk;
98 8 dinesha
 
99
//---------------------------------------------
100
//
101
// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
102
 
103
//--------------------------------------------
104
always @(posedge xtal_clk or negedge reset_n)
105
   begin // {
106
      if (!reset_n)
107
      begin // {
108
         pll_count <= 12'h9C4;
109
      end   // }                                                                 
110
      else if (configure_st)
111
      begin // {
112
         pll_count <= (fastsim_mode) ? 12'h040  :  12'h9C4;
113
      end // }
114
      else if (wait_pll_st)
115
      begin // {
116
         pll_count <= (pll_done) ? pll_count : (pll_count - 1'b1);
117
     end // }
118
   end // }
119
 
120
 
121
/************************************************
122
    PLL Timer Counter
123
************************************************/
124
 
125
always @(posedge xtal_clk or negedge reset_n)
126
begin
127
   if (!reset_n)
128
      pll_done <= 0;
129
   else if (pll_count == 16'h0)
130
      pll_done <= 1;
131
   else if (configure_st)
132
      pll_done <= 0;
133
end
134
 
135
 
136
/************************************************
137
  internally generated reset
138
************************************************/
139
always @(posedge xtal_clk or negedge reset_n )
140
begin
141
   if (!reset_n) begin
142 25 dinesha
      gen_resetn  <=  0;
143
      risc_reset  <=  1;
144 8 dinesha
   end else if(run_st ) begin
145 25 dinesha
      gen_resetn  <=  1;
146
      risc_reset  <=  0;
147
   end else if(slave_run_st ) begin
148
      gen_resetn  <=  1;
149
      risc_reset  <=  1; // Keet Risc in Reset
150 8 dinesha
   end else begin
151 25 dinesha
      gen_resetn  <=  0;
152
      risc_reset  <=  1;
153 8 dinesha
   end
154
end
155
 
156
 
157
/****************************************
158
    Reset State Machine
159
****************************************/
160
/*****************************************
161
   Define Clock Gen stat machine state
162
*****************************************/
163 25 dinesha
`define HARD_RESET      3'b000
164
`define CONFIGURE       3'b001
165
`define WAIT_PLL        3'b010
166
`define RUN             3'b011
167
`define SLAVE_RUN       3'b100
168 8 dinesha
 
169
assign hard_reset_st     = (clkgen_ps == `HARD_RESET);
170
assign configure_st      = (clkgen_ps == `CONFIGURE);
171
assign wait_pll_st       = (clkgen_ps == `WAIT_PLL);
172
assign run_st            = (clkgen_ps == `RUN);
173 25 dinesha
assign slave_run_st      = (clkgen_ps == `SLAVE_RUN);
174 8 dinesha
 
175
always @(posedge xtal_clk or negedge reset_n)
176
begin
177
   if (!reset_n) begin
178
      clkgen_ps <= `HARD_RESET;
179
   end
180
   else begin
181
      case (clkgen_ps)
182
         `HARD_RESET:
183
            clkgen_ps <= `CONFIGURE;
184
 
185
          `CONFIGURE:
186
             clkgen_ps <= `WAIT_PLL;
187
 
188
         `WAIT_PLL:
189 25 dinesha
           if (pll_done) begin
190
              if ( mastermode )
191
                             clkgen_ps <= `RUN;
192
                    else
193
                             clkgen_ps <= `SLAVE_RUN;
194
          end
195 8 dinesha
      endcase
196
   end
197
end
198
 
199
 
200
//----------------------------------
201
// Generate Application clock 125Mhz
202
//----------------------------------
203
 
204 57 dinesha
clk_ctl #(1) u_appclk (
205 8 dinesha
   // Outputs
206
       .clk_o         (app_clk),
207
   // Inputs
208
       .mclk          (pllout),
209
       .reset_n       (gen_resetn),
210
       .clk_div_ratio (2'b00)
211
   );
212
 
213
 
214
//----------------------------------
215
// Generate Uart Ref Clock clock 50Mhz
216 57 dinesha
// 200Mhz/(2+0) = 50Mhz
217 8 dinesha
// 250Mhz/(2+3) = 50Mhz
218
//----------------------------------
219
 
220 57 dinesha
clk_ctl #(2) u_uart_clk (
221 8 dinesha
   // Outputs
222
       .clk_o         (uart_ref_clk),
223
 
224
   // Inputs
225
       .mclk          (pllout      ),
226
       .reset_n       (gen_resetn  ),
227 57 dinesha
       .clk_div_ratio (3'b000      )
228 8 dinesha
   );
229
 
230
 
231
 
232
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.