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[/] [turbo8051/] [trunk/] [rtl/] [clkgen/] [clkgen.v] - Blame information for rev 57

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores clockgen Module                             ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module clkgen (
               reset_n      ,
               fastsim_mode ,
               mastermode   ,
               xtal_clk     ,
               clkout       ,
               gen_resetn   ,
               risc_reset   ,
               app_clk      ,
               uart_ref_clk
              );
 
 
 
input           reset_n        ; // Async reset signal
input         fastsim_mode   ; // fast sim mode = 1
input         mastermode     ; // 1 : Risc master mode
input           xtal_clk       ; // Xtal clock-25Mhx 
output        clkout         ; // clock output, 250Mhz
output        gen_resetn     ; // internally generated reset
output        risc_reset      ; // internally generated reset
output        app_clk        ; // application clock
output        uart_ref_clk   ; // uart 16x Ref clock
 
 
wire          hard_reset_st  ;
wire          configure_st   ;
wire          wait_pll_st    ;
wire          run_st         ;
wire          slave_run_st   ;
reg           pll_done       ;
reg [11:0]         pll_count      ;
reg [2:0]          clkgen_ps      ;
reg           gen_resetn     ; // internally generated reset
reg           risc_reset      ; // internally generated reset
 
 
assign        clkout = app_clk;
wire          pllout;
/***********************************************
 Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
*********************************************************/
/*******************
altera_stargate_pll u_pll (
        . areset     (!reset_n ),
        . inclk0     (xtal_clk),
        . c0         (pllout),
        . locked     ()
       );
*************************/
 
assign pllout = xtal_clk;
 
//---------------------------------------------
//
// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
 
//--------------------------------------------
always @(posedge xtal_clk or negedge reset_n)
   begin // {
      if (!reset_n)
      begin // {
         pll_count <= 12'h9C4;
      end   // }                                                                 
      else if (configure_st)
      begin // {
         pll_count <= (fastsim_mode) ? 12'h040  :  12'h9C4;
      end // }
      else if (wait_pll_st)
      begin // {
         pll_count <= (pll_done) ? pll_count : (pll_count - 1'b1);
     end // }
   end // }
 
 
/************************************************
    PLL Timer Counter
************************************************/
 
always @(posedge xtal_clk or negedge reset_n)
begin
   if (!reset_n)
      pll_done <= 0;
   else if (pll_count == 16'h0)
      pll_done <= 1;
   else if (configure_st)
      pll_done <= 0;
end
 
 
/************************************************
  internally generated reset
************************************************/
always @(posedge xtal_clk or negedge reset_n )
begin
   if (!reset_n) begin
      gen_resetn  <=  0;
      risc_reset  <=  1;
   end else if(run_st ) begin
      gen_resetn  <=  1;
      risc_reset  <=  0;
   end else if(slave_run_st ) begin
      gen_resetn  <=  1;
      risc_reset  <=  1; // Keet Risc in Reset
   end else begin
      gen_resetn  <=  0;
      risc_reset  <=  1;
   end
end
 
 
/****************************************
    Reset State Machine
****************************************/
/*****************************************
   Define Clock Gen stat machine state
*****************************************/
`define HARD_RESET      3'b000
`define CONFIGURE       3'b001
`define WAIT_PLL        3'b010
`define RUN             3'b011
`define SLAVE_RUN       3'b100
 
assign hard_reset_st     = (clkgen_ps == `HARD_RESET);
assign configure_st      = (clkgen_ps == `CONFIGURE);
assign wait_pll_st       = (clkgen_ps == `WAIT_PLL);
assign run_st            = (clkgen_ps == `RUN);
assign slave_run_st      = (clkgen_ps == `SLAVE_RUN);
 
always @(posedge xtal_clk or negedge reset_n)
begin
   if (!reset_n) begin
      clkgen_ps <= `HARD_RESET;
   end
   else begin
      case (clkgen_ps)
         `HARD_RESET:
            clkgen_ps <= `CONFIGURE;
 
          `CONFIGURE:
             clkgen_ps <= `WAIT_PLL;
 
         `WAIT_PLL:
           if (pll_done) begin
              if ( mastermode )
                             clkgen_ps <= `RUN;
                    else
                             clkgen_ps <= `SLAVE_RUN;
          end
      endcase
   end
end
 
 
//----------------------------------
// Generate Application clock 125Mhz
//----------------------------------
 
clk_ctl #(1) u_appclk (
   // Outputs
       .clk_o         (app_clk),
   // Inputs
       .mclk          (pllout),
       .reset_n       (gen_resetn),
       .clk_div_ratio (2'b00)
   );
 
 
//----------------------------------
// Generate Uart Ref Clock clock 50Mhz
// 200Mhz/(2+0) = 50Mhz
// 250Mhz/(2+3) = 50Mhz
//----------------------------------
 
clk_ctl #(2) u_uart_clk (
   // Outputs
       .clk_o         (uart_ref_clk),
 
   // Inputs
       .mclk          (pllout      ),
       .reset_n       (gen_resetn  ),
       .clk_div_ratio (3'b000      )
   );
 
 
 
endmodule

Line No.	Rev	Author	Line
1	8	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tubo 8051 cores clockgen Module ////`
4			`//// ////`
5			`//// This file is part of the Turbo 8051 cores project ////`
6			`//// http://www.opencores.org/cores/turbo8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Turbo 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`module clkgen (`
45			`reset_n ,`
46			`fastsim_mode ,`
47	25	dinesha	`mastermode ,`
48	8	dinesha	`xtal_clk ,`
49			`clkout ,`
50			`gen_resetn ,`
51	25	dinesha	`risc_reset ,`
52	8	dinesha	`app_clk ,`
53			`uart_ref_clk`
54			`);`
55
56
57
58			`input reset_n ; // Async reset signal`
59			`input fastsim_mode ; // fast sim mode = 1`
60	25	dinesha	`input mastermode ; // 1 : Risc master mode`
61	8	dinesha	`input xtal_clk ; // Xtal clock-25Mhx`
62			`output clkout ; // clock output, 250Mhz`
63			`output gen_resetn ; // internally generated reset`
64	25	dinesha	`output risc_reset ; // internally generated reset`
65	8	dinesha	`output app_clk ; // application clock`
66			`output uart_ref_clk ; // uart 16x Ref clock`
67
68
69			`wire hard_reset_st ;`
70			`wire configure_st ;`
71			`wire wait_pll_st ;`
72			`wire run_st ;`
73	25	dinesha	`wire slave_run_st ;`
74	8	dinesha	`reg pll_done ;`
75			`reg [11:0] pll_count ;`
76	25	dinesha	`reg [2:0] clkgen_ps ;`
77	8	dinesha	`reg gen_resetn ; // internally generated reset`
78	25	dinesha	`reg risc_reset ; // internally generated reset`
79	8	dinesha
80
81			`assign clkout = app_clk;`
82			`wire pllout;`
83			`/***********************************************`
84			`Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz`
85			`*********************************************************/`
86	57	dinesha	`/*******************`
87	8	dinesha	`altera_stargate_pll u_pll (`
88			`. areset (!reset_n ),`
89			`. inclk0 (xtal_clk),`
90			`. c0 (pllout),`
91			`. locked ()`
92			`);`
93	57	dinesha	`*************************/`
94	8	dinesha
95	57	dinesha	`assign pllout = xtal_clk;`
96	8	dinesha
97			`//---------------------------------------------`
98			`//`
99			`// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)`
100
101			`//--------------------------------------------`
102			`always @(posedge xtal_clk or negedge reset_n)`
103			`begin // {`
104			`if (!reset_n)`
105			`begin // {`
106			`pll_count <= 12'h9C4;`
107			`end // }`
108			`else if (configure_st)`
109			`begin // {`
110			`pll_count <= (fastsim_mode) ? 12'h040 : 12'h9C4;`
111			`end // }`
112			`else if (wait_pll_st)`
113			`begin // {`
114			`pll_count <= (pll_done) ? pll_count : (pll_count - 1'b1);`
115			`end // }`
116			`end // }`
117
118
119			`/************************************************`
120			`PLL Timer Counter`
121			`************************************************/`
122
123			`always @(posedge xtal_clk or negedge reset_n)`
124			`begin`
125			`if (!reset_n)`
126			`pll_done <= 0;`
127			`else if (pll_count == 16'h0)`
128			`pll_done <= 1;`
129			`else if (configure_st)`
130			`pll_done <= 0;`
131			`end`
132
133
134			`/************************************************`
135			`internally generated reset`
136			`************************************************/`
137			`always @(posedge xtal_clk or negedge reset_n )`
138			`begin`
139			`if (!reset_n) begin`
140	25	dinesha	`gen_resetn <= 0;`
141			`risc_reset <= 1;`
142	8	dinesha	`end else if(run_st ) begin`
143	25	dinesha	`gen_resetn <= 1;`
144			`risc_reset <= 0;`
145			`end else if(slave_run_st ) begin`
146			`gen_resetn <= 1;`
147			`risc_reset <= 1; // Keet Risc in Reset`
148	8	dinesha	`end else begin`
149	25	dinesha	`gen_resetn <= 0;`
150			`risc_reset <= 1;`
151	8	dinesha	`end`
152			`end`
153
154
155			`/****************************************`
156			`Reset State Machine`
157			`****************************************/`
158			`/*****************************************`
159			`Define Clock Gen stat machine state`
160			`*****************************************/`
161	25	dinesha	`define HARD_RESET 3'b000
162			`define CONFIGURE 3'b001
163			`define WAIT_PLL 3'b010
164			`define RUN 3'b011
165			`define SLAVE_RUN 3'b100
166	8	dinesha
167			assign hard_reset_st = (clkgen_ps == `HARD_RESET);
168			assign configure_st = (clkgen_ps == `CONFIGURE);
169			assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
170			assign run_st = (clkgen_ps == `RUN);
171	25	dinesha	assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
172	8	dinesha
173			`always @(posedge xtal_clk or negedge reset_n)`
174			`begin`
175			`if (!reset_n) begin`
176			clkgen_ps <= `HARD_RESET;
177			`end`
178			`else begin`
179			`case (clkgen_ps)`
180			`HARD_RESET:
181			clkgen_ps <= `CONFIGURE;
182
183			`CONFIGURE:
184			clkgen_ps <= `WAIT_PLL;
185
186			`WAIT_PLL:
187	25	dinesha	`if (pll_done) begin`
188			`if ( mastermode )`
189			clkgen_ps <= `RUN;
190			`else`
191			clkgen_ps <= `SLAVE_RUN;
192			`end`
193	8	dinesha	`endcase`
194			`end`
195			`end`
196
197
198			`//----------------------------------`
199			`// Generate Application clock 125Mhz`
200			`//----------------------------------`
201
202	57	dinesha	`clk_ctl #(1) u_appclk (`
203	8	dinesha	`// Outputs`
204			`.clk_o (app_clk),`
205			`// Inputs`
206			`.mclk (pllout),`
207			`.reset_n (gen_resetn),`
208			`.clk_div_ratio (2'b00)`
209			`);`
210
211
212			`//----------------------------------`
213			`// Generate Uart Ref Clock clock 50Mhz`
214	57	dinesha	`// 200Mhz/(2+0) = 50Mhz`
215	8	dinesha	`// 250Mhz/(2+3) = 50Mhz`
216			`//----------------------------------`
217
218	57	dinesha	`clk_ctl #(2) u_uart_clk (`
219	8	dinesha	`// Outputs`
220			`.clk_o (uart_ref_clk),`
221
222			`// Inputs`
223			`.mclk (pllout ),`
224			`.reset_n (gen_resetn ),`
225	57	dinesha	`.clk_div_ratio (3'b000 )`
226	8	dinesha	`);`
227
228
229
230			`endmodule`

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[/] [turbo8051/] [trunk/] [rtl/] [clkgen/] [clkgen.v] - Blame information for rev 57