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[/] [turbo8051/] [trunk/] [rtl/] [core/] [digital_core.v] - Blame information for rev 79

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`include "top_defines.v"
module digital_core  (
 
             reset_n                ,
             scan_mode              ,
             scan_enable             ,
             fastsim_mode           ,
             mastermode             ,
             xtal_clk               ,
             clkout                 ,
             reset_out_n            ,
 
        // Reg Bus Interface Signal
             ext_reg_cs             ,
             ext_reg_tid            ,
             ext_reg_wr             ,
             ext_reg_addr           ,
             ext_reg_wdata          ,
             ext_reg_be             ,
 
            // Outputs
             ext_reg_rdata          ,
             ext_reg_ack            ,
 
 
          // Line Side Interface TX Path
             phy_tx_en              ,
             phy_txd                ,
             phy_tx_clk             ,
 
          // Line Side Interface RX Path
             phy_rx_clk             ,
             phy_rx_dv              ,
             phy_rxd                ,
 
          //MDIO interface
             mdio_clk               ,
             mdio_in                ,
             mdio_out               ,
             mdio_out_en            ,
 
 
       // UART Line Interface
             si                     ,
             so                     ,
 
 
             spi_sck                ,
             spi_so                 ,
             spi_si                 ,
             spi_cs_n               ,
 
 
         // External ROM interface
             wb_xrom_adr            ,
             wb_xrom_ack            ,
             wb_xrom_err            ,
             wb_xrom_wr             ,
             wb_xrom_rdata          ,
             wb_xrom_wdata          ,
 
             wb_xrom_stb            ,
             wb_xrom_cyc            ,
 
         // External RAM interface
             wb_xram_adr            ,
             wb_xram_ack            ,
             wb_xram_err            ,
             wb_xram_wr             ,
             wb_xram_be             ,
             wb_xram_rdata          ,
             wb_xram_wdata          ,
 
             wb_xram_stb            ,
             wb_xram_cyc,
 
             ea_in
 
 
 
        );
 
 
//----------------------------------------
// Global Clock Defination
//----------------------------------------
input            reset_n               ; // Active Low Reset           
input            scan_mode             ; // scan mode
input            scan_enable           ; // scan enable
input            fastsim_mode          ; // Fast Sim Mode
input            mastermode            ; // 1 : Risc master mode
 
input            xtal_clk              ; // xtal clock 25Mhz
output           clkout                ; // clock output
output           reset_out_n           ; // clock output
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input            ext_reg_cs            ;
input            ext_reg_wr            ;
input [3:0]      ext_reg_tid           ;
input [14:0]     ext_reg_addr          ;
input [31:0]     ext_reg_wdata         ;
input [3:0]      ext_reg_be            ;
 
// Outputs
output [31:0]    ext_reg_rdata         ;
output           ext_reg_ack           ;
 
//----------------------------------------
// MAC Line Side Interface TX Path
//----------------------------------------
output           phy_tx_en              ; // MAC Tx Enable
output [7:0]     phy_txd                ; // MAC Tx Data
input           phy_tx_clk             ; // MAC Tx Clock
 
//----------------------------------------
// MAC Line Side Interface RX Path
//----------------------------------------
input           phy_rx_clk             ; // MAC Rx Clock
input           phy_rx_dv              ; // MAC Rx Dv
input [7:0]     phy_rxd                ; // MAC Rxd
 
//----------------------------------------
// MDIO interface
//----------------------------------------
output           mdio_clk              ; // MDIO Clock
input            mdio_in               ; // MDIO Data
output           mdio_out              ; // MDIO Data
output           mdio_out_en           ; // MDIO Data
 
 
//----------------------------------------
// UART Line Interface
//----------------------------------------
input            si                     ; // serial in
output           so                     ; // serial out
 
//----------------------------------------
// SPI Line Interface
//----------------------------------------
 
output           spi_sck                ; // clock
output           spi_so                 ; // data out
input            spi_si                 ; // data in
output  [3:0]    spi_cs_n               ; // chip select
 
//----------------------------------------
// 8051 core ROM related signals
//---------------------------------------
output [15:0]    wb_xrom_adr            ; // instruction address
input            wb_xrom_ack            ; // instruction acknowlage
output           wb_xrom_err            ; // instruction error
output           wb_xrom_wr             ; // instruction error
input  [31:0]    wb_xrom_rdata          ; // rom data input
output [31:0]    wb_xrom_wdata          ; // rom data input
 
output           wb_xrom_stb            ; // instruction strobe
output           wb_xrom_cyc            ; // instruction cycle
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
output [15:0]    wb_xram_adr            ; // data-ram address
input            wb_xram_ack            ; // data-ram acknowlage
output           wb_xram_err            ; // data-ram error
output           wb_xram_wr             ; // data-ram error
output [3:0]     wb_xram_be             ; // Byte enable
input  [31:0]    wb_xram_rdata          ; // ram data input
output [31:0]    wb_xram_wdata          ; // ram data input
 
output           wb_xram_stb            ; // data-ram strobe
output           wb_xram_cyc            ; // data-ram cycle
 
 
input            ea_in                  ; // input for external access (ea signal)
                                          // ea=0 program is in external rom
                                          // ea=1 program is in internal rom
//---------------------------------------------
// 8051 Instruction ROM interface
//---------------------------------------------
wire    [15:0]   wbi_risc_adr;
wire    [31:0]   wbi_risc_rdata;
 
 
//-----------------------------
// MAC Related wire Decleration
//-----------------------------
wire [8:0]       app_rxfifo_rddata_o    ;
wire [31:0]      app_rx_desc_data       ;
wire             mdio_out_en            ;
wire             mdio_out               ;
wire             gen_resetn             ;
 
 
//---------------------------------------------
// 8051 Instruction RAM interface
//---------------------------------------------
wire    [15:0]   wbd_risc_adr           ;
wire    [7:0]    wbd_risc_rdata         ;
wire    [7:0]    wbd_risc_wdata         ;
 
wire    [14:0]   reg_mac_addr           ;
wire    [31:0]   reg_mac_wdata          ;
wire    [3:0]    reg_mac_be             ;
wire    [31:0]   reg_mac_rdata          ;
wire             reg_mac_ack            ;
 
wire    [14:0]   reg_uart_addr          ;
wire    [31:0]   reg_uart_wdata         ;
wire    [3:0]    reg_uart_be            ;
wire    [31:0]   reg_uart_rdata         ;
wire             reg_uart_ack           ;
 
wire    [14:0]   reg_spi_addr           ;
wire    [31:0]   reg_spi_wdata          ;
wire    [3:0]    reg_spi_be             ;
wire    [31:0]   reg_spi_rdata          ;
wire             reg_spi_ack            ;
 
wire    [3:0]    wb_xrom_be            ;
wire    [3:0]    wb_xram_be            ;
 
wire    [7:0]    p0              ;
wire    [7:0]    p1              ;
wire    [7:0]    p2              ;
wire    [7:0]    p3              ;
 
wire [3:0]       wbgt_taddr      ;
wire [31:0]      wbgt_din        ;
wire [31:0]      wbgt_dout       ;
wire [12:0]      wbgt_addr       ;
wire [3:0]       wbgt_be         ;
wire             wbgt_we         ;
wire             wbgt_ack        ;
wire             wbgt_stb        ;
wire             wbgt_cyc        ;
 
wire [3:0]       wbgr_taddr      ;
wire [31:0]      wbgr_din        ;
wire [31:0]      wbgr_dout       ;
wire [12:0]      wbgr_addr       ;
wire [3:0]       wbgr_be         ;
wire             wbgr_we         ;
wire             wbgr_ack        ;
wire             wbgr_stb        ;
wire             wbgr_cyc        ;
 
wire [8:0]       app_txfifo_wrdata_i;
wire [15:0]      app_txfifo_addr;
wire [15:0]      app_rxfifo_addr;
wire [3:0]       tx_qcnt    ;
wire [3:0]       rx_qcnt    ;
 
wire tx_q_empty  = (tx_qcnt == 0);
wire rx_q_empty  = (rx_qcnt == 0);
 
wire [31:0] reg_rdata = (reg_mac_ack)  ? reg_mac_rdata :
                   (reg_uart_ack) ? reg_uart_rdata :
                   (reg_spi_ack)  ? reg_spi_rdata : 'h0;
 
wire reg_ack = reg_mac_ack | reg_uart_ack | reg_spi_ack;
 
 
assign reset_out_n = gen_resetn;
 
 
assign wb_xram_adr[15]    = 0;
assign wb_xram_adr[1:0]   = 2'b00;
assign wb_xrom_adr[15:13] = 0;
 
wire [9:0] cfg_tx_buf_qbase_addr;
wire [9:0] cfg_rx_buf_qbase_addr;
 
// QCounter Inc/dec generation
 
wire tx_qcnt_inc = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
wire tx_qcnt_dec = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
wire rx_qcnt_inc = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
wire rx_qcnt_dec = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
 
assign reg_mac_addr[1:0] = 2'b0;
assign reg_uart_addr[1:0] = 2'b0;
assign reg_spi_addr[1:0] = 2'b0;
//-------------------------------------------
// clock-gen  instantiation
//-------------------------------------------
clkgen u_clkgen (
               . reset_n                (reset_n               ),
               . fastsim_mode           (fastsim_mode          ),
               . mastermode             (mastermode            ),
               . xtal_clk               (xtal_clk              ),
               . clkout                 (clkout                ),
               . gen_resetn             (gen_resetn            ),
               . risc_reset             (risc_reset            ),
               . app_clk                (app_clk               ),
               . uart_ref_clk           (uart_clk_16x          )
 
              );
 
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0100 -- MAC core
// 4'b0011 -- UART
// 4'b0010 -- SPI core
// 4'b0001 -- External RAM
// 4'b0000 -- External ROM
//--------------------------------------------------------------
 
 
wire [31:0] wb_master2_rdata;
 
wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:
                           (wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:
                           (wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;
 
assign     wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:
                            (wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:
                            (wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:
                            wb_master2_rdata[31:24];
 
//------------------------------
// RISC Data Memory Map
// 0x0000 to 0x7FFFF  - Data Memory
// 0x8000 to 0x8FFF   - SPI 
// 0x9000 to 0x9FFF   - UART
// 0xA000 to 0xAFFF   - MAC Core
//-----------------------------
// 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0001 :
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;
 
wb_crossbar #(5,5,32,4,13,4) u_wb_crossbar (
 
              .rst_n                    (gen_resetn           ),
              .clk                      (app_clk              ),
 
 
    // Master Interface Signal
              .wbd_taddr_master         ({4'b0000,
                                          wbd_tar_id,
                                          ext_reg_tid,
                                          wbgt_taddr,
                                          wbgr_taddr}),
              .wbd_din_master           ({32'h0 ,
                                          {wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0]},
                                          ext_reg_wdata,
                                          wbgt_din,
                                          wbgr_din}
                                         ),
              .wbd_dout_master          ({wbi_risc_rdata,
                                          wb_master2_rdata,
                                          ext_reg_rdata,
                                          wbgt_dout,
                                          wbgr_dout}
                                           ),
              .wbd_adr_master           ({wbi_risc_adr[12:0],
                                          wbd_risc_adr[14:2],
                                          ext_reg_addr[14:2],
                                          wbgt_addr,
                                          wbgr_addr}
                                          ),
              .wbd_be_master            ({4'b1111,
                                          wb_master2_be,
                                          ext_reg_be,
                                          wbgt_be,
                                          wbgr_be}
                                           ),
              .wbd_we_master            ({1'b0,wbd_risc_we,ext_reg_wr,
                                         wbgt_we,wbgr_we}   ),
              .wbd_ack_master           ({wbi_risc_ack,
                                          wbd_risc_ack,
                                          ext_reg_ack,
                                          wbgt_ack,
                                          wbgr_ack} ),
              .wbd_stb_master           ({wbi_risc_stb,
                                          wbd_risc_stb,
                                          ext_reg_cs,
                                          wbgt_stb,
                                          wbgr_stb} ),
              .wbd_cyc_master           ({wbi_risc_stb|wbi_risc_ack,
                                          wbd_risc_stb|wbd_risc_ack,
                                          ext_reg_cs|ext_reg_ack,
                                          wbgt_cyc,wbgr_cyc}),
              .wbd_err_master           (),
              .wbd_rty_master           (),
 
    // Slave Interface Signal
              .wbd_din_slave            ({
                                          reg_mac_wdata,
                                          reg_uart_wdata,
                                          reg_spi_wdata,
                                          wb_xram_wdata,
                                          wb_xrom_wdata
                                          }),
              .wbd_dout_slave           ({
                                          reg_mac_rdata,
                                          reg_uart_rdata,
                                          reg_spi_rdata,
                                          {wb_xram_rdata},
                                          wb_xrom_rdata
                                         }),
              .wbd_adr_slave            ({reg_mac_addr[14:2],
                                          reg_uart_addr[14:2],
                                          reg_spi_addr[14:2],
                                          wb_xram_adr[14:2],
                                          wb_xrom_adr[12:0]}
                                        ),
              .wbd_be_slave             ({reg_mac_be,
                                          reg_uart_be,
                                          reg_spi_be,
                                          wb_xram_be,
                                          wb_xrom_be}
                                        ),
              .wbd_we_slave             ({reg_mac_wr,
                                          reg_uart_wr,
                                          reg_spi_wr,
                                          wb_xram_wr,
                                          wb_xrom_wr
                                          }),
              .wbd_ack_slave            ({reg_mac_ack,
                                          reg_uart_ack,
                                          reg_spi_ack,
                                          wb_xram_ack,
                                          wb_xrom_ack
                                         }),
              .wbd_stb_slave            ({reg_mac_cs,
                                          reg_uart_cs,
                                          reg_spi_cs,
                                          wb_xram_stb,
                                          wb_xrom_stb
                                         }),
              .wbd_cyc_slave            (),
              .wbd_err_slave            (),
              .wbd_rty_slave            ()
         );
 
 
//-------------------------------------------
// GMAC core instantiation
//-------------------------------------------
 
g_mac_top u_eth_dut (
 
          .scan_mode                    (1'b0                  ),
          .s_reset_n                    (gen_resetn            ),
          .tx_reset_n                   (gen_resetn            ),
          .rx_reset_n                   (gen_resetn            ),
          .reset_mdio_clk_n             (gen_resetn            ),
          .app_reset_n                  (gen_resetn            ),
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_mac_cs            ),
          . reg_wr                      (reg_mac_wr            ),
          . reg_addr                    (reg_mac_addr[5:2]     ),
          . reg_wdata                   (reg_mac_wdata         ),
          . reg_be                      (reg_mac_be            ),
 
            // Outputs
          . reg_rdata                   (reg_mac_rdata         ),
          . reg_ack                     (reg_mac_ack           ),
 
 
          .app_clk                      (app_clk               ),
 
          // Application RX FIFO Interface
          .app_txfifo_wren_i            (app_txfifo_wren_i   ),
          .app_txfifo_wrdata_i          (app_txfifo_wrdata_i ),
          .app_txfifo_addr              (app_txfifo_addr     ),
          .app_txfifo_full_o            (app_txfifo_full_o   ),
          .app_txfifo_afull_o           (app_txfifo_afull_o  ),
          .app_txfifo_space_o           (                    ),
 
          // Application TX FIFO Interface
          .app_rxfifo_rden_i            (app_rxfifo_rden_i   ),
          .app_rxfifo_empty_o           (app_rxfifo_empty_o  ),
          .app_rxfifo_aempty_o          (app_rxfifo_aempty_o ),
          .app_rxfifo_cnt_o             (                    ),
          .app_rxfifo_rdata_o           (app_rxfifo_rddata_o ),
          .app_rxfifo_addr              (app_rxfifo_addr     ),
 
          .app_rx_desc_req              (app_rx_desc_req     ),
          .app_rx_desc_ack              (app_rx_desc_ack     ),
          .app_rx_desc_discard          (app_rx_desc_discard ),
          .app_rx_desc_data             (app_rx_desc_data    ),
 
          // Line Side Interface TX Path
          .phy_tx_en                    (phy_tx_en           ),
          .phy_tx_er                    (                    ),
          .phy_txd                      (phy_txd             ),
          .phy_tx_clk                   (phy_tx_clk          ),
 
          // Line Side Interface RX Path
          .phy_rx_clk                   (phy_rx_clk          ),
          .phy_rx_er                    (1'b0                ),
          .phy_rx_dv                    (phy_rx_dv           ),
          .phy_rxd                      (phy_rxd             ),
          .phy_crs                      (1'b0                ),
 
          //MDIO interface
          .mdio_clk                     (mdio_clk            ),
          .mdio_in                      (mdio_in             ),
          .mdio_out_en                  (mdio_out_en         ),
          .mdio_out                     (mdio_out            ),
 
          // QCounter
          .rx_buf_qbase_addr            (cfg_rx_buf_qbase_addr),
          .tx_buf_qbase_addr            (cfg_tx_buf_qbase_addr),
 
          .tx_qcnt_inc                  (tx_qcnt_inc),
          .tx_qcnt_dec                  (tx_qcnt_dec),
          .rx_qcnt_inc                  (rx_qcnt_inc),
          .rx_qcnt_dec                  (rx_qcnt_dec),
          .tx_qcnt                      (tx_qcnt),
          .rx_qcnt                      (rx_qcnt)
 
 
       );
 
 
 
 
 
wb_rd_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_tx (
 
          .rst_n               ( gen_resetn         ),
          .clk                 ( app_clk            ),
 
    // descriptor handshake
          .cfg_desc_baddr      (cfg_tx_buf_qbase_addr),
          .desc_q_empty        (tx_q_empty           ),
 
    // Master Interface Signal
          .mem_taddr           ( 4'h1               ),
          .mem_full            (app_txfifo_full_o   ),
          .mem_afull           (app_txfifo_afull_o  ),
          .mem_wr              (app_txfifo_wren_i   ),
          .mem_din             (app_txfifo_wrdata_i ),
 
    // Slave Interface Signal
          .wbo_dout            ( wbgt_dout          ),
          .wbo_taddr           ( wbgt_taddr         ),
          .wbo_addr            ( wbgt_addr          ),
          .wbo_be              ( wbgt_be            ),
          .wbo_we              ( wbgt_we            ),
          .wbo_ack             ( wbgt_ack           ),
          .wbo_stb             ( wbgt_stb           ),
          .wbo_cyc             ( wbgt_cyc           ),
          .wbo_err             ( wbgt_err           ),
          .wbo_rty             ( wbgt_rty           )
         );
 
 
wb_wr_mem2mem #(.D_WD(32),.BE_WD(4),.ADR_WD(13),.TAR_WD(4)) u_wb_gmac_rx(
 
          .rst_n               ( gen_resetn   ),
          .clk                 ( app_clk      ),
 
 
    // Master Interface Signal
          .mem_taddr           ( 4'h1                 ),
          .mem_addr            (app_rxfifo_addr       ),
          .mem_empty           (app_rxfifo_empty_o    ),
          .mem_aempty          (app_rxfifo_aempty_o   ),
          .mem_rd              (app_rxfifo_rden_i     ),
          .mem_dout            (app_rxfifo_rddata_o[7:0]),
          .mem_eop             (app_rxfifo_rddata_o[8]),
 
          .cfg_desc_baddr      (cfg_rx_buf_qbase_addr ),
          .desc_req            (app_rx_desc_req       ),
          .desc_ack            (app_rx_desc_ack       ),
          .desc_disccard       (app_rx_desc_discard   ),
          .desc_data           (app_rx_desc_data      ),
    // Slave Interface Signal
          .wbo_din             ( wbgr_din     ),
          .wbo_taddr           ( wbgr_taddr   ),
          .wbo_addr            ( wbgr_addr    ),
          .wbo_be              ( wbgr_be      ),
          .wbo_we              ( wbgr_we      ),
          .wbo_ack             ( wbgr_ack     ),
          .wbo_stb             ( wbgr_stb     ),
          .wbo_cyc             ( wbgr_cyc     ),
          .wbo_err             ( wbgr_err     ),
          .wbo_rty             ( wbgr_rty     )
         );
 
//-------------------------------------
// UART core instantiation
//-------------------------------------
 
uart_core  u_uart_core
 
     (
          . line_reset_n                (gen_resetn            ),
          . line_clk_16x                (uart_clk_16x          ),
 
          . app_reset_n                 (gen_resetn            ),
          . app_clk                     (app_clk               ),
 
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_uart_cs           ),
          . reg_wr                      (reg_uart_wr           ),
          . reg_addr                    (reg_uart_addr[5:2]    ),
          . reg_wdata                   (reg_uart_wdata        ),
          . reg_be                      (reg_uart_be           ),
 
            // Outputs
          . reg_rdata                   (reg_uart_rdata        ),
          . reg_ack                     (reg_uart_ack          ),
 
 
 
       // Line Interface
          . si                          (si                    ),
          . so                          (so                    )
 
     );
 
 
//--------------------------------
// SPI core instantiation
//--------------------------------
 
 
spi_core u_spi_core (
 
          . clk                         (app_clk               ),
          . reset_n                     (gen_resetn            ),
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_spi_cs            ),
          . reg_wr                      (reg_spi_wr            ),
          . reg_addr                    (reg_spi_addr[5:2]     ),
          . reg_wdata                   (reg_spi_wdata         ),
          . reg_be                      (reg_spi_be            ),
 
            // Outputs
          . reg_rdata                   (reg_spi_rdata         ),
          . reg_ack                     (reg_spi_ack           ),
 
 
          . sck                         (spi_sck               ),
          . so                          (spi_so                ),
          . si                          (spi_si                ),
          . cs_n                        (spi_cs_n              )
 
           );
 
 
 
oc8051_top u_8051_core (
          . wb_rst_i                    (risc_reset            ),
          . wb_clk_i                    (app_clk               ),
 
//interface to instruction rom
          . wbi_adr_o                   (wbi_risc_adr          ),
          . wbi_dat_i                   (wbi_risc_rdata        ),
          . wbi_stb_o                   (wbi_risc_stb          ),
          . wbi_ack_i                   (wbi_risc_ack          ),
          . wbi_cyc_o                   (wbi_risc_cyc          ),
          . wbi_err_i                   (wbi_risc_err          ),
 
//interface to data ram
          . wbd_dat_i                   (wbd_risc_rdata        ),
          . wbd_dat_o                   (wbd_risc_wdata        ),
          . wbd_adr_o                   (wbd_risc_adr          ),
          . wbd_we_o                    (wbd_risc_we           ),
          . wbd_ack_i                   (wbd_risc_ack          ),
          . wbd_stb_o                   (wbd_risc_stb          ),
          . wbd_cyc_o                   (wbd_risc_cyc          ),
          . wbd_err_i                   (wbd_risc_err          ),
 
// interrupt interface
          . int0_i                      (                      ),
          . int1_i                      (                      ),
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_i                         ( p0                    ),
          .p0_o                         ( p0                    ),
        `endif
 
        `ifdef OC8051_PORT1
           .p1_i                        ( p1                    ),
           .p1_o                        ( p1                    ),
        `endif
 
        `ifdef OC8051_PORT2
           .p2_i                        ( p2                    ),
           .p2_o                        ( p2                    ),
        `endif
 
        `ifdef OC8051_PORT3
           .p3_i                        ( p3                    ),
           .p3_o                        ( p3                    ),
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
           .rxd_i                       (                      ),
           .txd_o                       (                      ),
        `endif
 
// counter interface
        `ifdef OC8051_TC01
           .t0_i                        (                      ),
           .t1_i                        (                      ),
        `endif
 
        `ifdef OC8051_TC2
           .t2_i                        (                      ),
           .t2ex_i                      (                      ),
        `endif
 
// BIST
`ifdef OC8051_BIST
            .scanb_rst                  (                      ),
            .scanb_clk                  (                      ),
            .scanb_si                   (                      ),
            .scanb_so                   (                      ),
            .scanb_en                   (                      ),
`endif
// external access (active low)
            .ea_in                      (ea_in                 )
         );
 
endmodule

Line No.	Rev	Author	Line
1	13	dinesha
2	76	dinesha	`include "top_defines.v"
3			`module digital_core (`
4	13	dinesha
5			`reset_n ,`
6	76	dinesha	`scan_mode ,`
7			`scan_enable ,`
8	13	dinesha	`fastsim_mode ,`
9	26	dinesha	`mastermode ,`
10	13	dinesha	`xtal_clk ,`
11			`clkout ,`
12			`reset_out_n ,`
13
14			`// Reg Bus Interface Signal`
15			`ext_reg_cs ,`
16			`ext_reg_tid ,`
17			`ext_reg_wr ,`
18			`ext_reg_addr ,`
19			`ext_reg_wdata ,`
20			`ext_reg_be ,`
21
22			`// Outputs`
23			`ext_reg_rdata ,`
24			`ext_reg_ack ,`
25
26
27			`// Line Side Interface TX Path`
28			`phy_tx_en ,`
29			`phy_txd ,`
30			`phy_tx_clk ,`
31
32			`// Line Side Interface RX Path`
33			`phy_rx_clk ,`
34			`phy_rx_dv ,`
35			`phy_rxd ,`
36
37			`//MDIO interface`
38	76	dinesha	`mdio_clk ,`
39			`mdio_in ,`
40			`mdio_out ,`
41			`mdio_out_en ,`
42	13	dinesha
43
44			`// UART Line Interface`
45			`si ,`
46			`so ,`
47
48
49			`spi_sck ,`
50			`spi_so ,`
51			`spi_si ,`
52			`spi_cs_n ,`
53
54
55			`// External ROM interface`
56			`wb_xrom_adr ,`
57			`wb_xrom_ack ,`
58			`wb_xrom_err ,`
59			`wb_xrom_wr ,`
60			`wb_xrom_rdata ,`
61			`wb_xrom_wdata ,`
62
63			`wb_xrom_stb ,`
64			`wb_xrom_cyc ,`
65
66			`// External RAM interface`
67			`wb_xram_adr ,`
68			`wb_xram_ack ,`
69			`wb_xram_err ,`
70			`wb_xram_wr ,`
71	50	dinesha	`wb_xram_be ,`
72	13	dinesha	`wb_xram_rdata ,`
73			`wb_xram_wdata ,`
74
75			`wb_xram_stb ,`
76			`wb_xram_cyc,`
77
78			`ea_in`
79
80
81
82			`);`
83
84
85			`//----------------------------------------`
86			`// Global Clock Defination`
87			`//----------------------------------------`
88			`input reset_n ; // Active Low Reset`
89	76	dinesha	`input scan_mode ; // scan mode`
90			`input scan_enable ; // scan enable`
91	13	dinesha	`input fastsim_mode ; // Fast Sim Mode`
92	26	dinesha	`input mastermode ; // 1 : Risc master mode`
93
94	13	dinesha	`input xtal_clk ; // xtal clock 25Mhz`
95			`output clkout ; // clock output`
96			`output reset_out_n ; // clock output`
97
98			`//---------------------------------`
99			`// Reg Bus Interface Signal`
100			`//---------------------------------`
101			`input ext_reg_cs ;`
102			`input ext_reg_wr ;`
103			`input [3:0] ext_reg_tid ;`
104	56	dinesha	`input [14:0] ext_reg_addr ;`
105	13	dinesha	`input [31:0] ext_reg_wdata ;`
106			`input [3:0] ext_reg_be ;`
107
108			`// Outputs`
109			`output [31:0] ext_reg_rdata ;`
110			`output ext_reg_ack ;`
111
112			`//----------------------------------------`
113			`// MAC Line Side Interface TX Path`
114			`//----------------------------------------`
115			`output phy_tx_en ; // MAC Tx Enable`
116			`output [7:0] phy_txd ; // MAC Tx Data`
117	75	dinesha	`input phy_tx_clk ; // MAC Tx Clock`
118	13	dinesha
119			`//----------------------------------------`
120			`// MAC Line Side Interface RX Path`
121			`//----------------------------------------`
122	75	dinesha	`input phy_rx_clk ; // MAC Rx Clock`
123	76	dinesha	`input phy_rx_dv ; // MAC Rx Dv`
124			`input [7:0] phy_rxd ; // MAC Rxd`
125	13	dinesha
126			`//----------------------------------------`
127			`// MDIO interface`
128			`//----------------------------------------`
129	76	dinesha	`output mdio_clk ; // MDIO Clock`
130			`input mdio_in ; // MDIO Data`
131			`output mdio_out ; // MDIO Data`
132			`output mdio_out_en ; // MDIO Data`
133	13	dinesha
134
135			`//----------------------------------------`
136			`// UART Line Interface`
137			`//----------------------------------------`
138			`input si ; // serial in`
139			`output so ; // serial out`
140
141			`//----------------------------------------`
142			`// SPI Line Interface`
143			`//----------------------------------------`
144
145			`output spi_sck ; // clock`
146			`output spi_so ; // data out`
147			`input spi_si ; // data in`
148			`output [3:0] spi_cs_n ; // chip select`
149
150			`//----------------------------------------`
151			`// 8051 core ROM related signals`
152			`//---------------------------------------`
153			`output [15:0] wb_xrom_adr ; // instruction address`
154			`input wb_xrom_ack ; // instruction acknowlage`
155			`output wb_xrom_err ; // instruction error`
156			`output wb_xrom_wr ; // instruction error`
157			`input [31:0] wb_xrom_rdata ; // rom data input`
158			`output [31:0] wb_xrom_wdata ; // rom data input`
159
160			`output wb_xrom_stb ; // instruction strobe`
161			`output wb_xrom_cyc ; // instruction cycle`
162
163
164			`//----------------------------------------`
165			`// 8051 core RAM related signals`
166			`//---------------------------------------`
167			`output [15:0] wb_xram_adr ; // data-ram address`
168			`input wb_xram_ack ; // data-ram acknowlage`
169			`output wb_xram_err ; // data-ram error`
170			`output wb_xram_wr ; // data-ram error`
171	50	dinesha	`output [3:0] wb_xram_be ; // Byte enable`
172			`input [31:0] wb_xram_rdata ; // ram data input`
173			`output [31:0] wb_xram_wdata ; // ram data input`
174	13	dinesha
175			`output wb_xram_stb ; // data-ram strobe`
176			`output wb_xram_cyc ; // data-ram cycle`
177
178
179			`input ea_in ; // input for external access (ea signal)`
180			`// ea=0 program is in external rom`
181			`// ea=1 program is in internal rom`
182			`//---------------------------------------------`
183			`// 8051 Instruction ROM interface`
184			`//---------------------------------------------`
185			`wire [15:0] wbi_risc_adr;`
186			`wire [31:0] wbi_risc_rdata;`
187
188
189			`//-----------------------------`
190			`// MAC Related wire Decleration`
191			`//-----------------------------`
192			`wire [8:0] app_rxfifo_rddata_o ;`
193	50	dinesha	`wire [31:0] app_rx_desc_data ;`
194	13	dinesha	`wire mdio_out_en ;`
195			`wire mdio_out ;`
196			`wire gen_resetn ;`
197
198
199			`//---------------------------------------------`
200			`// 8051 Instruction RAM interface`
201			`//---------------------------------------------`
202			`wire [15:0] wbd_risc_adr ;`
203			`wire [7:0] wbd_risc_rdata ;`
204			`wire [7:0] wbd_risc_wdata ;`
205
206	56	dinesha	`wire [14:0] reg_mac_addr ;`
207	13	dinesha	`wire [31:0] reg_mac_wdata ;`
208			`wire [3:0] reg_mac_be ;`
209			`wire [31:0] reg_mac_rdata ;`
210			`wire reg_mac_ack ;`
211
212	56	dinesha	`wire [14:0] reg_uart_addr ;`
213	13	dinesha	`wire [31:0] reg_uart_wdata ;`
214			`wire [3:0] reg_uart_be ;`
215			`wire [31:0] reg_uart_rdata ;`
216			`wire reg_uart_ack ;`
217
218	56	dinesha	`wire [14:0] reg_spi_addr ;`
219	13	dinesha	`wire [31:0] reg_spi_wdata ;`
220			`wire [3:0] reg_spi_be ;`
221			`wire [31:0] reg_spi_rdata ;`
222			`wire reg_spi_ack ;`
223
224			`wire [3:0] wb_xrom_be ;`
225			`wire [3:0] wb_xram_be ;`
226
227	21	dinesha	`wire [7:0] p0 ;`
228			`wire [7:0] p1 ;`
229			`wire [7:0] p2 ;`
230			`wire [7:0] p3 ;`
231	13	dinesha
232	21	dinesha	`wire [3:0] wbgt_taddr ;`
233			`wire [31:0] wbgt_din ;`
234			`wire [31:0] wbgt_dout ;`
235			`wire [12:0] wbgt_addr ;`
236			`wire [3:0] wbgt_be ;`
237			`wire wbgt_we ;`
238			`wire wbgt_ack ;`
239			`wire wbgt_stb ;`
240			`wire wbgt_cyc ;`
241
242			`wire [3:0] wbgr_taddr ;`
243			`wire [31:0] wbgr_din ;`
244			`wire [31:0] wbgr_dout ;`
245			`wire [12:0] wbgr_addr ;`
246			`wire [3:0] wbgr_be ;`
247			`wire wbgr_we ;`
248			`wire wbgr_ack ;`
249			`wire wbgr_stb ;`
250			`wire wbgr_cyc ;`
251
252			`wire [8:0] app_txfifo_wrdata_i;`
253			`wire [15:0] app_txfifo_addr;`
254			`wire [15:0] app_rxfifo_addr;`
255	50	dinesha	`wire [3:0] tx_qcnt ;`
256			`wire [3:0] rx_qcnt ;`
257	21	dinesha
258	50	dinesha	`wire tx_q_empty = (tx_qcnt == 0);`
259			`wire rx_q_empty = (rx_qcnt == 0);`
260	21	dinesha
261	75	dinesha	`wire [31:0] reg_rdata = (reg_mac_ack) ? reg_mac_rdata :`
262	13	dinesha	`(reg_uart_ack) ? reg_uart_rdata :`
263			`(reg_spi_ack) ? reg_spi_rdata : 'h0;`
264
265	75	dinesha	`wire reg_ack = reg_mac_ack \| reg_uart_ack \| reg_spi_ack;`
266	13	dinesha
267
268			`assign reset_out_n = gen_resetn;`
269
270
271	50	dinesha	`assign wb_xram_adr[15] = 0;`
272			`assign wb_xram_adr[1:0] = 2'b00;`
273	13	dinesha	`assign wb_xrom_adr[15:13] = 0;`
274
275	50	dinesha	`wire [9:0] cfg_tx_buf_qbase_addr;`
276			`wire [9:0] cfg_rx_buf_qbase_addr;`
277
278			`// QCounter Inc/dec generation`
279
280	56	dinesha	`wire tx_qcnt_inc = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);`
281			`wire tx_qcnt_dec = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);`
282			`wire rx_qcnt_inc = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);`
283			`wire rx_qcnt_dec = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);`
284	50	dinesha
285	61	dinesha	`assign reg_mac_addr[1:0] = 2'b0;`
286			`assign reg_uart_addr[1:0] = 2'b0;`
287			`assign reg_spi_addr[1:0] = 2'b0;`
288	13	dinesha	`//-------------------------------------------`
289			`// clock-gen instantiation`
290			`//-------------------------------------------`
291			`clkgen u_clkgen (`
292			`. reset_n (reset_n ),`
293			`. fastsim_mode (fastsim_mode ),`
294	26	dinesha	`. mastermode (mastermode ),`
295	13	dinesha	`. xtal_clk (xtal_clk ),`
296			`. clkout (clkout ),`
297			`. gen_resetn (gen_resetn ),`
298	26	dinesha	`. risc_reset (risc_reset ),`
299	13	dinesha	`. app_clk (app_clk ),`
300			`. uart_ref_clk (uart_clk_16x )`
301
302			`);`
303
304			`//--------------------------------------------------------------`
305			`// Target ID Mapping`
306			`// 4'b0100 -- MAC core`
307			`// 4'b0011 -- UART`
308			`// 4'b0010 -- SPI core`
309			`// 4'b0001 -- External RAM`
310			`// 4'b0000 -- External ROM`
311			`//--------------------------------------------------------------`
312
313
314			`wire [31:0] wb_master2_rdata;`
315
316			`wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:`
317			`(wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:`
318			`(wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;`
319
320			`assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:`
321			`(wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:`
322			`(wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:`
323			`wb_master2_rdata[31:24];`
324
325	53	dinesha	`//------------------------------`
326			`// RISC Data Memory Map`
327			`// 0x0000 to 0x7FFFF - Data Memory`
328			`// 0x8000 to 0x8FFF - SPI`
329			`// 0x9000 to 0x9FFF - UART`
330			`// 0xA000 to 0xAFFF - MAC Core`
331			`//-----------------------------`
332			`//`
333			`wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 :`
334			`(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :`
335			`(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;`
336	13	dinesha
337	21	dinesha	`wb_crossbar #(5,5,32,4,13,4) u_wb_crossbar (`
338	13	dinesha
339			`.rst_n (gen_resetn ),`
340			`.clk (app_clk ),`
341
342
343			`// Master Interface Signal`
344			`.wbd_taddr_master ({4'b0000,`
345			`wbd_tar_id,`
346	21	dinesha	`ext_reg_tid,`
347			`wbgt_taddr,`
348			`wbgr_taddr}),`
349	13	dinesha	`.wbd_din_master ({32'h0 ,`
350			`{wbd_risc_wdata[7:0],`
351			`wbd_risc_wdata[7:0],`
352			`wbd_risc_wdata[7:0],`
353			`wbd_risc_wdata[7:0]},`
354	21	dinesha	`ext_reg_wdata,`
355			`wbgt_din,`
356			`wbgr_din}`
357			`),`
358	13	dinesha	`.wbd_dout_master ({wbi_risc_rdata,`
359			`wb_master2_rdata,`
360	21	dinesha	`ext_reg_rdata,`
361			`wbgt_dout,`
362			`wbgr_dout}`
363			`),`
364	13	dinesha	`.wbd_adr_master ({wbi_risc_adr[12:0],`
365	56	dinesha	`wbd_risc_adr[14:2],`
366			`ext_reg_addr[14:2],`
367	21	dinesha	`wbgt_addr,`
368			`wbgr_addr}`
369			`),`
370	13	dinesha	`.wbd_be_master ({4'b1111,`
371			`wb_master2_be,`
372	21	dinesha	`ext_reg_be,`
373			`wbgt_be,`
374			`wbgr_be}`
375			`),`
376			`.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr,`
377			`wbgt_we,wbgr_we} ),`
378	13	dinesha	`.wbd_ack_master ({wbi_risc_ack,`
379			`wbd_risc_ack,`
380	21	dinesha	`ext_reg_ack,`
381			`wbgt_ack,`
382			`wbgr_ack} ),`
383	13	dinesha	`.wbd_stb_master ({wbi_risc_stb,`
384			`wbd_risc_stb,`
385	21	dinesha	`ext_reg_cs,`
386			`wbgt_stb,`
387			`wbgr_stb} ),`
388	13	dinesha	`.wbd_cyc_master ({wbi_risc_stb\|wbi_risc_ack,`
389			`wbd_risc_stb\|wbd_risc_ack,`
390	21	dinesha	`ext_reg_cs\|ext_reg_ack,`
391			`wbgt_cyc,wbgr_cyc}),`
392	13	dinesha	`.wbd_err_master (),`
393			`.wbd_rty_master (),`
394
395			`// Slave Interface Signal`
396			`.wbd_din_slave ({`
397			`reg_mac_wdata,`
398			`reg_uart_wdata,`
399			`reg_spi_wdata,`
400			`wb_xram_wdata,`
401			`wb_xrom_wdata`
402			`}),`
403			`.wbd_dout_slave ({`
404			`reg_mac_rdata,`
405			`reg_uart_rdata,`
406			`reg_spi_rdata,`
407	50	dinesha	`{wb_xram_rdata},`
408	13	dinesha	`wb_xrom_rdata`
409			`}),`
410	56	dinesha	`.wbd_adr_slave ({reg_mac_addr[14:2],`
411			`reg_uart_addr[14:2],`
412			`reg_spi_addr[14:2],`
413	26	dinesha	`wb_xram_adr[14:2],`
414	13	dinesha	`wb_xrom_adr[12:0]}`
415			`),`
416			`.wbd_be_slave ({reg_mac_be,`
417			`reg_uart_be,`
418			`reg_spi_be,`
419			`wb_xram_be,`
420			`wb_xrom_be}`
421			`),`
422			`.wbd_we_slave ({reg_mac_wr,`
423			`reg_uart_wr,`
424			`reg_spi_wr,`
425			`wb_xram_wr,`
426			`wb_xrom_wr`
427			`}),`
428			`.wbd_ack_slave ({reg_mac_ack,`
429			`reg_uart_ack,`
430			`reg_spi_ack,`
431			`wb_xram_ack,`
432			`wb_xrom_ack`
433			`}),`
434			`.wbd_stb_slave ({reg_mac_cs,`
435			`reg_uart_cs,`
436			`reg_spi_cs,`
437			`wb_xram_stb,`
438			`wb_xrom_stb`
439			`}),`
440			`.wbd_cyc_slave (),`
441			`.wbd_err_slave (),`
442			`.wbd_rty_slave ()`
443			`);`
444
445
446			`//-------------------------------------------`
447			`// GMAC core instantiation`
448			`//-------------------------------------------`
449
450			`g_mac_top u_eth_dut (`
451
452			`.scan_mode (1'b0 ),`
453			`.s_reset_n (gen_resetn ),`
454			`.tx_reset_n (gen_resetn ),`
455			`.rx_reset_n (gen_resetn ),`
456			`.reset_mdio_clk_n (gen_resetn ),`
457			`.app_reset_n (gen_resetn ),`
458
459			`// Reg Bus Interface Signal`
460			`. reg_cs (reg_mac_cs ),`
461			`. reg_wr (reg_mac_wr ),`
462	57	dinesha	`. reg_addr (reg_mac_addr[5:2] ),`
463	13	dinesha	`. reg_wdata (reg_mac_wdata ),`
464			`. reg_be (reg_mac_be ),`
465
466			`// Outputs`
467			`. reg_rdata (reg_mac_rdata ),`
468			`. reg_ack (reg_mac_ack ),`
469
470
471			`.app_clk (app_clk ),`
472
473			`// Application RX FIFO Interface`
474	21	dinesha	`.app_txfifo_wren_i (app_txfifo_wren_i ),`
475			`.app_txfifo_wrdata_i (app_txfifo_wrdata_i ),`
476	50	dinesha	`.app_txfifo_addr (app_txfifo_addr ),`
477	21	dinesha	`.app_txfifo_full_o (app_txfifo_full_o ),`
478			`.app_txfifo_afull_o (app_txfifo_afull_o ),`
479	50	dinesha	`.app_txfifo_space_o ( ),`
480	13	dinesha
481			`// Application TX FIFO Interface`
482	21	dinesha	`.app_rxfifo_rden_i (app_rxfifo_rden_i ),`
483	50	dinesha	`.app_rxfifo_empty_o (app_rxfifo_empty_o ),`
484			`.app_rxfifo_aempty_o (app_rxfifo_aempty_o ),`
485			`.app_rxfifo_cnt_o ( ),`
486			`.app_rxfifo_rdata_o (app_rxfifo_rddata_o ),`
487			`.app_rxfifo_addr (app_rxfifo_addr ),`
488	13	dinesha
489	50	dinesha	`.app_rx_desc_req (app_rx_desc_req ),`
490			`.app_rx_desc_ack (app_rx_desc_ack ),`
491			`.app_rx_desc_discard (app_rx_desc_discard ),`
492			`.app_rx_desc_data (app_rx_desc_data ),`
493	13	dinesha
494			`// Line Side Interface TX Path`
495	50	dinesha	`.phy_tx_en (phy_tx_en ),`
496			`.phy_tx_er ( ),`
497			`.phy_txd (phy_txd ),`
498			`.phy_tx_clk (phy_tx_clk ),`
499	13	dinesha
500			`// Line Side Interface RX Path`

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[/] [turbo8051/] [trunk/] [rtl/] [core/] [digital_core.v] - Blame information for rev 79