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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [crc32/] [g_rx_crc32.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores MAC Interface Module                        ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
/***************************************************************
  Description:
  rx_crc32.v: This block contains the crc32 checker.
 * CRC is generated in the receive data when mi2rc_rcv_valid is asserted.
 * For the recieve data. crc_ok indicates whenther the packet was
 * good or bad.
 * The 32-bit crc shift register is reset to all 1's when
 * mi2rc_strt_rcv is asserted.
 
 *********************************************************************/
module g_rx_crc32 (
              // CRC Valid signal to rx_fsm
              rc2rf_crc_ok,
 
              // Global Signals
              phy_rx_clk,
              reset_n,
              // CRC Data signals
              mi2rc_strt_rcv,
              mi2rc_rcv_valid,
              mi2rc_rx_byte
              );
 
  // defx[ine inputs and outputs.
 
  output        rc2rf_crc_ok;            // asserted when crc check is ok. to rx.
 
  input         phy_rx_clk;              // serial clock from phy.
  input         reset_n;             // global asynchronous reset.
 
  input         mi2rc_rcv_valid;        // when asserted, crc is computed on 
                                   // rx_crc_data. from rx.
  input         mi2rc_strt_rcv;      // when asserted, crc shift register is
                                   // reset to all 1's. from rx.
  input [7:0]    mi2rc_rx_byte;       // receive data. from rx.
 
 
 
 
  // reg/wire declarations for primary outputs.
  wire          rc2rf_crc_ok;
 
  // define constants and parameters here.
  // define local signals here.
 
  wire [7:0]     crc_in;
  wire          gen_crc;
  reg [31:0]     current_crc, next_crc;
  reg           crc_ok_ul;
 
  wire [31:0]   rx_fcs;
 
  // code starts here.
 
  // select either rx_crc_data or tx_data as the input to crc generator.
  assign crc_in = mi2rc_rx_byte;
 
  // enable crc generator 
 
  assign gen_crc = mi2rc_rcv_valid ; // 
 
  // 32-bit crc shift register for crc calculation.
 
  always @(posedge phy_rx_clk or negedge reset_n)
    begin
      if (!reset_n)
        begin
          current_crc <= 32'hffffffff;
        end
      else
        begin
          if (mi2rc_strt_rcv)
            begin
              current_crc <= 32'hffffffff;
            end
          else if (gen_crc)  // generate crc 
            begin
              current_crc <= next_crc;
            end // else: !if(tx_reset_crc || mi2rc_strt_rcv)
        end // else: !if(!reset_n)
    end // always @ (posedge phy_rx_clk or negedge reset_n)
 
  // combinational logic to generate next_crc
 
  always @(current_crc or crc_in)
    begin
 
      next_crc[0]  = current_crc[8]  ^ current_crc[2] ^ crc_in[2];
            next_crc[1]  = current_crc[9]  ^ current_crc[0] ^ crc_in[0] ^
                           current_crc[3]  ^ crc_in[3];
            next_crc[2]  = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^
                           current_crc[1]  ^ crc_in[1] ^ current_crc[4]  ^
                                 crc_in[4];
            next_crc[3]  = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^
                           current_crc[2]  ^ crc_in[2] ^ current_crc[5]  ^
                                 crc_in[5];
            next_crc[4]  = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^
                           current_crc[3] ^ crc_in[3] ^ current_crc[6]  ^
                                 current_crc[0] ^ crc_in[0] ^ crc_in[6];
            next_crc[5]  = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^
                           current_crc[4] ^ crc_in[4] ^ current_crc[7]  ^
                                 current_crc[1] ^ crc_in[1] ^ crc_in[7];
            next_crc[6]  = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^
                           current_crc[5] ^ crc_in[5];
            next_crc[7]  = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^
                           current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                 crc_in[6];
            next_crc[8]  = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^
                           current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                           crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                                 crc_in[1] ^ crc_in[7];
            next_crc[9]  = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^
                           current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                           crc_in[7];
            next_crc[10]  = current_crc[18] ^ current_crc[2] ^ crc_in[2];
            next_crc[11]  = current_crc[19] ^ current_crc[3] ^ crc_in[3];
            next_crc[12]  = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[4] ^ crc_in[4];
            next_crc[13]  = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1] ^ crc_in[1] ^ current_crc[5]  ^
                                  crc_in[5];
            next_crc[14]  = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1] ^ crc_in[1] ^ current_crc[2]  ^
                                  crc_in[2] ^ current_crc[6] ^ current_crc[0]  ^
                                  crc_in[0] ^ crc_in[6];
            next_crc[15]  = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[7] ^ current_crc[1]  ^
                                  crc_in[1] ^ crc_in[7];
            next_crc[16]  = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[4] ^ crc_in[4];
            next_crc[17]  = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
                                  current_crc[5] ^ crc_in[5];
            next_crc[18]  = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[4]  ^
                                  crc_in[4] ^ current_crc[5] ^ crc_in[5]  ^
                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                  crc_in[6];
            next_crc[19]  = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[5] ^ crc_in[5]  ^
                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                  crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                                  crc_in[1] ^ crc_in[7];
            next_crc[20]  = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                  crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                                  crc_in[1] ^ crc_in[7];
            next_crc[21]  = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^
                      current_crc[2] ^ crc_in[2] ^ current_crc[4]  ^
                      crc_in[4] ^ current_crc[5] ^ crc_in[5]  ^
                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                      crc_in[7];
            next_crc[22]  = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^
                      current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                      crc_in[3] ^ current_crc[5] ^ crc_in[5]  ^
                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6];
            next_crc[23]  = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^
                      current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
                      crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                      crc_in[1] ^ crc_in[7];
            next_crc[24]  = current_crc[0] ^ crc_in[0] ^ current_crc[1]  ^
                      crc_in[1] ^ current_crc[2] ^ crc_in[2]    ^
                      current_crc[4] ^ crc_in[4] ^ current_crc[5]  ^
                      crc_in[5] ^ current_crc[7] ^ current_crc[1]  ^
                      crc_in[1] ^ crc_in[7];
            next_crc[25]  = current_crc[1] ^ crc_in[1] ^ current_crc[2]  ^
                            crc_in[2] ^ current_crc[3] ^ crc_in[3]    ^
                      current_crc[5] ^ crc_in[5] ^ current_crc[6]  ^
                      current_crc[0]  ^ crc_in[0] ^ crc_in[6];
            next_crc[26]  = current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                      crc_in[3] ^ current_crc[4] ^ crc_in[4]    ^
                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6]  ^ current_crc[7] ^ current_crc[1] ^
                      crc_in[1]  ^ crc_in[7];
            next_crc[27]  = current_crc[3] ^ crc_in[3] ^ current_crc[4]  ^
                      crc_in[4] ^ current_crc[5] ^ crc_in[5]    ^
                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                      crc_in[7];
            next_crc[28]  = current_crc[4] ^crc_in[4] ^ current_crc[5]   ^
                      crc_in[5] ^ current_crc[6] ^ current_crc[0]  ^
                      crc_in[0] ^ crc_in[6];
            next_crc[29]  = current_crc[5] ^ crc_in[5] ^ current_crc[6]  ^
                      current_crc[0] ^ crc_in[0] ^ crc_in[6]    ^
                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                      crc_in[7];
            next_crc[30]  = current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                      crc_in[1] ^ crc_in[7];
            next_crc[31]  = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
                      crc_in[7];
    end   // always
 
assign rx_fcs[0] = current_crc[31];
assign rx_fcs[1] = current_crc[30];
assign rx_fcs[2] = current_crc[29];
assign rx_fcs[3] = current_crc[28];
assign rx_fcs[4] = current_crc[27];
assign rx_fcs[5] = current_crc[26];
assign rx_fcs[6] = current_crc[25];
assign rx_fcs[7] = current_crc[24];
assign rx_fcs[8] = current_crc[23];
assign rx_fcs[9] = current_crc[22];
assign rx_fcs[10] = current_crc[21];
assign rx_fcs[11] = current_crc[20];
assign rx_fcs[12] = current_crc[19];
assign rx_fcs[13] = current_crc[18];
assign rx_fcs[14] = current_crc[17];
assign rx_fcs[15] = current_crc[16];
assign rx_fcs[16] = current_crc[15];
assign rx_fcs[17] = current_crc[14];
assign rx_fcs[18] = current_crc[13];
assign rx_fcs[19] = current_crc[12];
assign rx_fcs[20] = current_crc[11];
assign rx_fcs[21] = current_crc[10];
assign rx_fcs[22] = current_crc[9];
assign rx_fcs[23] = current_crc[8];
assign rx_fcs[24] = current_crc[7];
assign rx_fcs[25] = current_crc[6];
assign rx_fcs[26] = current_crc[5];
assign rx_fcs[27] = current_crc[4];
assign rx_fcs[28] = current_crc[3];
assign rx_fcs[29] = current_crc[2];
assign rx_fcs[30] = current_crc[1];
assign rx_fcs[31] = current_crc[0];
 
  always @(rx_fcs)
    begin
      if (rx_fcs == 32'hc704dd7b)
        crc_ok_ul = 1;
      else
        crc_ok_ul = 0;
    end  // always
 
 
 assign rc2rf_crc_ok = crc_ok_ul;
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 

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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [crc32/] [g_rx_crc32.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tubo 8051 cores MAC Interface Module ////`
4			`//// ////`
5			`//// This file is part of the Turbo 8051 cores project ////`
6			`//// http://www.opencores.org/cores/turbo8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Turbo 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`/***************************************************************`
44			`Description:`
45			`rx_crc32.v: This block contains the crc32 checker.`
46			`* CRC is generated in the receive data when mi2rc_rcv_valid is asserted.`
47			`* For the recieve data. crc_ok indicates whenther the packet was`
48			`* good or bad.`
49			`* The 32-bit crc shift register is reset to all 1's when`
50			`* mi2rc_strt_rcv is asserted.`
51
52			`*********************************************************************/`
53			`module g_rx_crc32 (`
54			`// CRC Valid signal to rx_fsm`
55			`rc2rf_crc_ok,`
56
57			`// Global Signals`
58			`phy_rx_clk,`
59			`reset_n,`
60			`// CRC Data signals`
61			`mi2rc_strt_rcv,`
62			`mi2rc_rcv_valid,`
63			`mi2rc_rx_byte`
64			`);`
65
66			`// defx[ine inputs and outputs.`
67
68			`output rc2rf_crc_ok; // asserted when crc check is ok. to rx.`
69
70			`input phy_rx_clk; // serial clock from phy.`
71			`input reset_n; // global asynchronous reset.`
72
73			`input mi2rc_rcv_valid; // when asserted, crc is computed on`
74			`// rx_crc_data. from rx.`
75			`input mi2rc_strt_rcv; // when asserted, crc shift register is`
76			`// reset to all 1's. from rx.`
77			`input [7:0] mi2rc_rx_byte; // receive data. from rx.`
78
79
80
81
82			`// reg/wire declarations for primary outputs.`
83			`wire rc2rf_crc_ok;`
84
85			`// define constants and parameters here.`
86			`// define local signals here.`
87
88			`wire [7:0] crc_in;`
89			`wire gen_crc;`
90			`reg [31:0] current_crc, next_crc;`
91			`reg crc_ok_ul;`
92
93			`wire [31:0] rx_fcs;`
94
95			`// code starts here.`
96
97			`// select either rx_crc_data or tx_data as the input to crc generator.`
98			`assign crc_in = mi2rc_rx_byte;`
99
100			`// enable crc generator`
101
102			`assign gen_crc = mi2rc_rcv_valid ; //`
103
104			`// 32-bit crc shift register for crc calculation.`
105
106			`always @(posedge phy_rx_clk or negedge reset_n)`
107			`begin`
108			`if (!reset_n)`
109			`begin`
110			`current_crc <= 32'hffffffff;`
111			`end`
112			`else`
113			`begin`
114			`if (mi2rc_strt_rcv)`
115			`begin`
116			`current_crc <= 32'hffffffff;`
117			`end`
118			`else if (gen_crc) // generate crc`
119			`begin`
120			`current_crc <= next_crc;`
121			`end // else: !if(tx_reset_crc \|\| mi2rc_strt_rcv)`
122			`end // else: !if(!reset_n)`
123			`end // always @ (posedge phy_rx_clk or negedge reset_n)`
124
125			`// combinational logic to generate next_crc`
126
127			`always @(current_crc or crc_in)`
128			`begin`
129
130			`next_crc[0] = current_crc[8] ^ current_crc[2] ^ crc_in[2];`
131			`next_crc[1] = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^`
132			`current_crc[3] ^ crc_in[3];`
133			`next_crc[2] = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^`
134			`current_crc[1] ^ crc_in[1] ^ current_crc[4] ^`
135			`crc_in[4];`
136			`next_crc[3] = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^`
137			`current_crc[2] ^ crc_in[2] ^ current_crc[5] ^`
138			`crc_in[5];`
139			`next_crc[4] = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^`
140			`current_crc[3] ^ crc_in[3] ^ current_crc[6] ^`
141			`current_crc[0] ^ crc_in[0] ^ crc_in[6];`
142			`next_crc[5] = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^`
143			`current_crc[4] ^ crc_in[4] ^ current_crc[7] ^`
144			`current_crc[1] ^ crc_in[1] ^ crc_in[7];`
145			`next_crc[6] = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^`
146			`current_crc[5] ^ crc_in[5];`
147			`next_crc[7] = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^`
148			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
149			`crc_in[6];`
150			`next_crc[8] = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^`
151			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
152			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
153			`crc_in[1] ^ crc_in[7];`
154			`next_crc[9] = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^`
155			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
156			`crc_in[7];`
157			`next_crc[10] = current_crc[18] ^ current_crc[2] ^ crc_in[2];`
158			`next_crc[11] = current_crc[19] ^ current_crc[3] ^ crc_in[3];`
159			`next_crc[12] = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^`
160			`current_crc[4] ^ crc_in[4];`
161			`next_crc[13] = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^`
162			`current_crc[1] ^ crc_in[1] ^ current_crc[5] ^`
163			`crc_in[5];`
164			`next_crc[14] = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^`
165			`current_crc[1] ^ crc_in[1] ^ current_crc[2] ^`
166			`crc_in[2] ^ current_crc[6] ^ current_crc[0] ^`
167			`crc_in[0] ^ crc_in[6];`
168			`next_crc[15] = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^`
169			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
170			`crc_in[3] ^ current_crc[7] ^ current_crc[1] ^`
171			`crc_in[1] ^ crc_in[7];`
172			`next_crc[16] = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^`
173			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
174			`crc_in[3] ^ current_crc[4] ^ crc_in[4];`
175			`next_crc[17] = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^`
176			`current_crc[1] ^ crc_in[1] ^ current_crc[3] ^`
177			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
178			`current_crc[5] ^ crc_in[5];`
179			`next_crc[18] = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^`
180			`current_crc[2] ^ crc_in[2] ^ current_crc[4] ^`
181			`crc_in[4] ^ current_crc[5] ^ crc_in[5] ^`
182			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
183			`crc_in[6];`
184			`next_crc[19] = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^`
185			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
186			`crc_in[3] ^ current_crc[5] ^ crc_in[5] ^`
187			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
188			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
189			`crc_in[1] ^ crc_in[7];`
190			`next_crc[20] = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^`
191			`current_crc[1] ^ crc_in[1] ^ current_crc[3] ^`
192			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
193			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
194			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
195			`crc_in[1] ^ crc_in[7];`
196			`next_crc[21] = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^`
197			`current_crc[2] ^ crc_in[2] ^ current_crc[4] ^`
198			`crc_in[4] ^ current_crc[5] ^ crc_in[5] ^`
199			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
200			`crc_in[7];`
201			`next_crc[22] = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^`
202			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
203			`crc_in[3] ^ current_crc[5] ^ crc_in[5] ^`
204			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
205			`crc_in[6];`
206			`next_crc[23] = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^`
207			`current_crc[1] ^ crc_in[1] ^ current_crc[3] ^`
208			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
209			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
210			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
211			`crc_in[1] ^ crc_in[7];`
212			`next_crc[24] = current_crc[0] ^ crc_in[0] ^ current_crc[1] ^`
213			`crc_in[1] ^ current_crc[2] ^ crc_in[2] ^`
214			`current_crc[4] ^ crc_in[4] ^ current_crc[5] ^`
215			`crc_in[5] ^ current_crc[7] ^ current_crc[1] ^`
216			`crc_in[1] ^ crc_in[7];`
217			`next_crc[25] = current_crc[1] ^ crc_in[1] ^ current_crc[2] ^`
218			`crc_in[2] ^ current_crc[3] ^ crc_in[3] ^`
219			`current_crc[5] ^ crc_in[5] ^ current_crc[6] ^`
220			`current_crc[0] ^ crc_in[0] ^ crc_in[6];`
221			`next_crc[26] = current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
222			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
223			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
224			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
225			`crc_in[1] ^ crc_in[7];`
226			`next_crc[27] = current_crc[3] ^ crc_in[3] ^ current_crc[4] ^`
227			`crc_in[4] ^ current_crc[5] ^ crc_in[5] ^`
228			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
229			`crc_in[7];`
230			`next_crc[28] = current_crc[4] ^crc_in[4] ^ current_crc[5] ^`
231			`crc_in[5] ^ current_crc[6] ^ current_crc[0] ^`
232			`crc_in[0] ^ crc_in[6];`
233			`next_crc[29] = current_crc[5] ^ crc_in[5] ^ current_crc[6] ^`
234			`current_crc[0] ^ crc_in[0] ^ crc_in[6] ^`
235			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
236			`crc_in[7];`
237			`next_crc[30] = current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
238			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
239			`crc_in[1] ^ crc_in[7];`
240			`next_crc[31] = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
241			`crc_in[7];`
242			`end // always`
243
244			`assign rx_fcs[0] = current_crc[31];`
245			`assign rx_fcs[1] = current_crc[30];`
246			`assign rx_fcs[2] = current_crc[29];`
247			`assign rx_fcs[3] = current_crc[28];`
248			`assign rx_fcs[4] = current_crc[27];`
249			`assign rx_fcs[5] = current_crc[26];`
250			`assign rx_fcs[6] = current_crc[25];`
251			`assign rx_fcs[7] = current_crc[24];`
252			`assign rx_fcs[8] = current_crc[23];`
253			`assign rx_fcs[9] = current_crc[22];`
254			`assign rx_fcs[10] = current_crc[21];`
255			`assign rx_fcs[11] = current_crc[20];`
256			`assign rx_fcs[12] = current_crc[19];`
257			`assign rx_fcs[13] = current_crc[18];`
258			`assign rx_fcs[14] = current_crc[17];`
259			`assign rx_fcs[15] = current_crc[16];`
260			`assign rx_fcs[16] = current_crc[15];`
261			`assign rx_fcs[17] = current_crc[14];`
262			`assign rx_fcs[18] = current_crc[13];`
263			`assign rx_fcs[19] = current_crc[12];`
264			`assign rx_fcs[20] = current_crc[11];`
265			`assign rx_fcs[21] = current_crc[10];`
266			`assign rx_fcs[22] = current_crc[9];`
267			`assign rx_fcs[23] = current_crc[8];`
268			`assign rx_fcs[24] = current_crc[7];`
269			`assign rx_fcs[25] = current_crc[6];`
270			`assign rx_fcs[26] = current_crc[5];`
271			`assign rx_fcs[27] = current_crc[4];`
272			`assign rx_fcs[28] = current_crc[3];`
273			`assign rx_fcs[29] = current_crc[2];`
274			`assign rx_fcs[30] = current_crc[1];`
275			`assign rx_fcs[31] = current_crc[0];`
276
277			`always @(rx_fcs)`
278			`begin`
279			`if (rx_fcs == 32'hc704dd7b)`
280			`crc_ok_ul = 1;`
281			`else`
282			`crc_ok_ul = 0;`
283			`end // always`
284
285
286			`assign rc2rf_crc_ok = crc_ok_ul;`
287
288
289			`endmodule`
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