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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [crc32/] [g_tx_crc32.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores MAC Interface Module                        ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
/***************************************************************
  Description:
  crc_32.v: This block contains the tx_crc32 generator.
            CRC is generated on the tx data when gen_tx_crc asserted.
            The 32-bit crc shift register is reset to all 1's when either
            tx_reset_crc asserted
 
 *********************************************************************/
module g_tx_crc32 (
              // List of outputs.
              tx_fcs,
 
              // List of inputs
              gen_tx_crc,
              tx_reset_crc,
              tx_data,
              sclk,
              reset_n);
 
  // defx[ine inputs and outputs.
 
  input         gen_tx_crc;        // when asserted, crc is generated on the
                                   // tx_data[3:0]. 
  input         tx_reset_crc;      // when asserted, crc shift register is
                                   // reset to all 1's. from link_phy_intfc.
  input [7:0]    tx_data;           // trasnmit data.
  input         sclk;              // serial clock from phy.
  input         reset_n;             // global asynchronous reset.
 
 
  output [31:0]  tx_fcs;       // 32-bit crc for tx_data. to link_phy_intfc.
 
 
  // reg/wire declarations for primary outputs.
  wire [31:0]    tx_fcs;
 
  // define constants and parameters here.
 
  // define local signals here.
 
  wire [7:0]     crc_in;
  wire          gen_crc;
  wire[7:0]     tx_data_in;
  wire          carry0,carry1,carry2,carry3;
  wire          carry4,carry5,carry6,carry7;
  reg [31:0]     current_crc, next_crc;
 
  // code starts here.
  assign tx_data_in = tx_data;
  assign crc_in = tx_data_in;
 
  assign gen_crc = gen_tx_crc;
 
  // 32-bit crc shift register for crc calculation.
 
  always @(posedge sclk or negedge reset_n)
    begin
      if (!reset_n)
        begin
          current_crc <= 32'hffffffff;
        end
      else
        begin
          if (tx_reset_crc )
            begin
              current_crc <= 32'hffffffff;
            end
          else if (gen_crc)  // generate crc 
            begin
              current_crc <= next_crc;
            end // else: !if(tx_reset_crc )
        end // else: !if(reset_n)
    end // always @ (posedge sclk or negedge reset_n)
 
  // combinational logic to generate next_crc
 
  always @(current_crc or crc_in)
    begin
 
      next_crc[0]  = current_crc[8] ^ current_crc[2] ^ crc_in[2];
            next_crc[1]  = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^
                           current_crc[3] ^ crc_in[3];
            next_crc[2]  = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^
                           current_crc[1] ^ crc_in[1] ^ current_crc[4]  ^
                                 crc_in[4];
            next_crc[3]  = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^
                           current_crc[2] ^ crc_in[2] ^ current_crc[5]  ^
                                 crc_in[5];
            next_crc[4]  = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^
                           current_crc[3] ^ crc_in[3] ^ current_crc[6]  ^
                                 current_crc[0] ^ crc_in[0] ^ crc_in[6];
            next_crc[5]  = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^
                           current_crc[4] ^ crc_in[4] ^ current_crc[7]  ^
                                 current_crc[1] ^ crc_in[1] ^ crc_in[7];
            next_crc[6]  = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^
                           current_crc[5] ^ crc_in[5];
            next_crc[7]  = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^
                           current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                 crc_in[6];
            next_crc[8]  = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^
                           current_crc[6]  ^ current_crc[0] ^ crc_in[0]  ^
                                 crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                                 crc_in[1] ^ crc_in[7];
            next_crc[9]  = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^
                           current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                                 crc_in[7];
            next_crc[10]  = current_crc[18] ^ current_crc[2] ^ crc_in[2];
            next_crc[11]  = current_crc[19] ^ current_crc[3] ^ crc_in[3];
            next_crc[12]  = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[4]  ^ crc_in[4];
            next_crc[13]  = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1]  ^ crc_in[1] ^ current_crc[5]  ^
                                  crc_in[5];
            next_crc[14]  = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1] ^ crc_in[1] ^ current_crc[2]  ^
                            crc_in[2] ^ current_crc[6] ^ current_crc[0]  ^
                                  crc_in[0] ^ crc_in[6];
            next_crc[15]  = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[7] ^ current_crc[1]  ^
                                  crc_in[1] ^ crc_in[7];
            next_crc[16]  = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[4] ^ crc_in[4];
            next_crc[17]  = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
                                  current_crc[5] ^ crc_in[5];
            next_crc[18]  = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[4]  ^
                                  crc_in[4] ^ current_crc[5] ^ crc_in[5]  ^
                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                  crc_in[6];
            next_crc[19]  = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[5] ^ crc_in[5]  ^
                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                  crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                                  crc_in[1] ^ crc_in[7];
            next_crc[20]  = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^
                            current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
                                  crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                                  crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                                  crc_in[1] ^ crc_in[7];
            next_crc[21]  = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^
                      current_crc[2] ^ crc_in[2] ^ current_crc[4]  ^
                      crc_in[4] ^ current_crc[5] ^ crc_in[5]  ^
                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                      crc_in[7];
            next_crc[22]  = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^
                      current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                      crc_in[3] ^ current_crc[5] ^ crc_in[5]  ^
                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6];
            next_crc[23]  = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^
                      current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
                      crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                      crc_in[1] ^ crc_in[7];
            next_crc[24]  = current_crc[0] ^ crc_in[0] ^ current_crc[1]  ^
                      crc_in[1] ^ current_crc[2] ^ crc_in[2]    ^
                      current_crc[4] ^ crc_in[4] ^ current_crc[5]  ^
                      crc_in[5] ^ current_crc[7] ^ current_crc[1]  ^
                      crc_in[1] ^ crc_in[7];
            next_crc[25]  = current_crc[1] ^ crc_in[1] ^ current_crc[2]  ^
                            crc_in[2] ^ current_crc[3] ^ crc_in[3]    ^
                      current_crc[5] ^ crc_in[5] ^ current_crc[6]  ^
                      current_crc[0]  ^ crc_in[0] ^ crc_in[6];
            next_crc[26]  = current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
                      crc_in[3] ^ current_crc[4] ^ crc_in[4]    ^
                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6]  ^ current_crc[7] ^ current_crc[1] ^
                      crc_in[1]  ^ crc_in[7];
            next_crc[27]  = current_crc[3] ^ crc_in[3] ^ current_crc[4]  ^
                      crc_in[4] ^ current_crc[5] ^ crc_in[5]    ^
                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                      crc_in[7];
            next_crc[28]  = current_crc[4] ^crc_in[4] ^ current_crc[5]   ^
                      crc_in[5] ^ current_crc[6] ^ current_crc[0]  ^
                      crc_in[0] ^ crc_in[6];
            next_crc[29]  = current_crc[5] ^ crc_in[5] ^ current_crc[6]  ^
                      current_crc[0] ^ crc_in[0] ^ crc_in[6]    ^
                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
                      crc_in[7];
            next_crc[30]  = current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
                      crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
                      crc_in[1] ^ crc_in[7];
            next_crc[31]  = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
                      crc_in[7];
    end   // always
 
//  assign tx_fcs = ~current_crc;
  assign tx_fcs[0] = !current_crc[0];
  assign tx_fcs[1] = !current_crc[1];
  assign tx_fcs[2] = !current_crc[2];
  assign tx_fcs[3] = !current_crc[3];
  assign tx_fcs[4] = !current_crc[4];
  assign tx_fcs[5] = !current_crc[5];
  assign tx_fcs[6] = !current_crc[6];
  assign tx_fcs[7] = !current_crc[7];
  assign tx_fcs[8] = !current_crc[8];
  assign tx_fcs[9] = !current_crc[9];
  assign tx_fcs[10] = !current_crc[10];
  assign tx_fcs[11] = !current_crc[11];
  assign tx_fcs[12] = !current_crc[12];
  assign tx_fcs[13] = !current_crc[13];
  assign tx_fcs[14] = !current_crc[14];
  assign tx_fcs[15] = !current_crc[15];
  assign tx_fcs[16] = !current_crc[16];
  assign tx_fcs[17] = !current_crc[17];
  assign tx_fcs[18] = !current_crc[18];
  assign tx_fcs[19] = !current_crc[19];
  assign tx_fcs[20] = !current_crc[20];
  assign tx_fcs[21] = !current_crc[21];
  assign tx_fcs[22] = !current_crc[22];
  assign tx_fcs[23] = !current_crc[23];
  assign tx_fcs[24] = !current_crc[24];
  assign tx_fcs[25] = !current_crc[25];
  assign tx_fcs[26] = !current_crc[26];
  assign tx_fcs[27] = !current_crc[27];
  assign tx_fcs[28] = !current_crc[28];
  assign tx_fcs[29] = !current_crc[29];
  assign tx_fcs[30] = !current_crc[30];
  assign tx_fcs[31] = !current_crc[31];
 
endmodule

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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [crc32/] [g_tx_crc32.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tubo 8051 cores MAC Interface Module ////`
4			`//// ////`
5			`//// This file is part of the Turbo 8051 cores project ////`
6			`//// http://www.opencores.org/cores/turbo8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Turbo 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`/***************************************************************`
45			`Description:`
46			`crc_32.v: This block contains the tx_crc32 generator.`
47			`CRC is generated on the tx data when gen_tx_crc asserted.`
48			`The 32-bit crc shift register is reset to all 1's when either`
49			`tx_reset_crc asserted`
50
51			`*********************************************************************/`
52			`module g_tx_crc32 (`
53			`// List of outputs.`
54			`tx_fcs,`
55
56			`// List of inputs`
57			`gen_tx_crc,`
58			`tx_reset_crc,`
59			`tx_data,`
60			`sclk,`
61			`reset_n);`
62
63			`// defx[ine inputs and outputs.`
64
65			`input gen_tx_crc; // when asserted, crc is generated on the`
66			`// tx_data[3:0].`
67			`input tx_reset_crc; // when asserted, crc shift register is`
68			`// reset to all 1's. from link_phy_intfc.`
69			`input [7:0] tx_data; // trasnmit data.`
70			`input sclk; // serial clock from phy.`
71			`input reset_n; // global asynchronous reset.`
72
73
74			`output [31:0] tx_fcs; // 32-bit crc for tx_data. to link_phy_intfc.`
75
76
77			`// reg/wire declarations for primary outputs.`
78			`wire [31:0] tx_fcs;`
79
80			`// define constants and parameters here.`
81
82			`// define local signals here.`
83
84			`wire [7:0] crc_in;`
85			`wire gen_crc;`
86			`wire[7:0] tx_data_in;`
87			`wire carry0,carry1,carry2,carry3;`
88			`wire carry4,carry5,carry6,carry7;`
89			`reg [31:0] current_crc, next_crc;`
90
91			`// code starts here.`
92			`assign tx_data_in = tx_data;`
93			`assign crc_in = tx_data_in;`
94
95			`assign gen_crc = gen_tx_crc;`
96
97			`// 32-bit crc shift register for crc calculation.`
98
99			`always @(posedge sclk or negedge reset_n)`
100			`begin`
101			`if (!reset_n)`
102			`begin`
103			`current_crc <= 32'hffffffff;`
104			`end`
105			`else`
106			`begin`
107			`if (tx_reset_crc )`
108			`begin`
109			`current_crc <= 32'hffffffff;`
110			`end`
111			`else if (gen_crc) // generate crc`
112			`begin`
113			`current_crc <= next_crc;`
114			`end // else: !if(tx_reset_crc )`
115			`end // else: !if(reset_n)`
116			`end // always @ (posedge sclk or negedge reset_n)`
117
118			`// combinational logic to generate next_crc`
119
120			`always @(current_crc or crc_in)`
121			`begin`
122
123			`next_crc[0] = current_crc[8] ^ current_crc[2] ^ crc_in[2];`
124			`next_crc[1] = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^`
125			`current_crc[3] ^ crc_in[3];`
126			`next_crc[2] = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^`
127			`current_crc[1] ^ crc_in[1] ^ current_crc[4] ^`
128			`crc_in[4];`
129			`next_crc[3] = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^`
130			`current_crc[2] ^ crc_in[2] ^ current_crc[5] ^`
131			`crc_in[5];`
132			`next_crc[4] = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^`
133			`current_crc[3] ^ crc_in[3] ^ current_crc[6] ^`
134			`current_crc[0] ^ crc_in[0] ^ crc_in[6];`
135			`next_crc[5] = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^`
136			`current_crc[4] ^ crc_in[4] ^ current_crc[7] ^`
137			`current_crc[1] ^ crc_in[1] ^ crc_in[7];`
138			`next_crc[6] = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^`
139			`current_crc[5] ^ crc_in[5];`
140			`next_crc[7] = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^`
141			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
142			`crc_in[6];`
143			`next_crc[8] = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^`
144			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
145			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
146			`crc_in[1] ^ crc_in[7];`
147			`next_crc[9] = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^`
148			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
149			`crc_in[7];`
150			`next_crc[10] = current_crc[18] ^ current_crc[2] ^ crc_in[2];`
151			`next_crc[11] = current_crc[19] ^ current_crc[3] ^ crc_in[3];`
152			`next_crc[12] = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^`
153			`current_crc[4] ^ crc_in[4];`
154			`next_crc[13] = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^`
155			`current_crc[1] ^ crc_in[1] ^ current_crc[5] ^`
156			`crc_in[5];`
157			`next_crc[14] = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^`
158			`current_crc[1] ^ crc_in[1] ^ current_crc[2] ^`
159			`crc_in[2] ^ current_crc[6] ^ current_crc[0] ^`
160			`crc_in[0] ^ crc_in[6];`
161			`next_crc[15] = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^`
162			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
163			`crc_in[3] ^ current_crc[7] ^ current_crc[1] ^`
164			`crc_in[1] ^ crc_in[7];`
165			`next_crc[16] = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^`
166			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
167			`crc_in[3] ^ current_crc[4] ^ crc_in[4];`
168			`next_crc[17] = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^`
169			`current_crc[1] ^ crc_in[1] ^ current_crc[3] ^`
170			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
171			`current_crc[5] ^ crc_in[5];`
172			`next_crc[18] = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^`
173			`current_crc[2] ^ crc_in[2] ^ current_crc[4] ^`
174			`crc_in[4] ^ current_crc[5] ^ crc_in[5] ^`
175			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
176			`crc_in[6];`
177			`next_crc[19] = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^`
178			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
179			`crc_in[3] ^ current_crc[5] ^ crc_in[5] ^`
180			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
181			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
182			`crc_in[1] ^ crc_in[7];`
183			`next_crc[20] = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^`
184			`current_crc[1] ^ crc_in[1] ^ current_crc[3] ^`
185			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
186			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
187			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
188			`crc_in[1] ^ crc_in[7];`
189			`next_crc[21] = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^`
190			`current_crc[2] ^ crc_in[2] ^ current_crc[4] ^`
191			`crc_in[4] ^ current_crc[5] ^ crc_in[5] ^`
192			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
193			`crc_in[7];`
194			`next_crc[22] = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^`
195			`current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
196			`crc_in[3] ^ current_crc[5] ^ crc_in[5] ^`
197			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
198			`crc_in[6];`
199			`next_crc[23] = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^`
200			`current_crc[1] ^ crc_in[1] ^ current_crc[3] ^`
201			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
202			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
203			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
204			`crc_in[1] ^ crc_in[7];`
205			`next_crc[24] = current_crc[0] ^ crc_in[0] ^ current_crc[1] ^`
206			`crc_in[1] ^ current_crc[2] ^ crc_in[2] ^`
207			`current_crc[4] ^ crc_in[4] ^ current_crc[5] ^`
208			`crc_in[5] ^ current_crc[7] ^ current_crc[1] ^`
209			`crc_in[1] ^ crc_in[7];`
210			`next_crc[25] = current_crc[1] ^ crc_in[1] ^ current_crc[2] ^`
211			`crc_in[2] ^ current_crc[3] ^ crc_in[3] ^`
212			`current_crc[5] ^ crc_in[5] ^ current_crc[6] ^`
213			`current_crc[0] ^ crc_in[0] ^ crc_in[6];`
214			`next_crc[26] = current_crc[2] ^ crc_in[2] ^ current_crc[3] ^`
215			`crc_in[3] ^ current_crc[4] ^ crc_in[4] ^`
216			`current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
217			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
218			`crc_in[1] ^ crc_in[7];`
219			`next_crc[27] = current_crc[3] ^ crc_in[3] ^ current_crc[4] ^`
220			`crc_in[4] ^ current_crc[5] ^ crc_in[5] ^`
221			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
222			`crc_in[7];`
223			`next_crc[28] = current_crc[4] ^crc_in[4] ^ current_crc[5] ^`
224			`crc_in[5] ^ current_crc[6] ^ current_crc[0] ^`
225			`crc_in[0] ^ crc_in[6];`
226			`next_crc[29] = current_crc[5] ^ crc_in[5] ^ current_crc[6] ^`
227			`current_crc[0] ^ crc_in[0] ^ crc_in[6] ^`
228			`current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
229			`crc_in[7];`
230			`next_crc[30] = current_crc[6] ^ current_crc[0] ^ crc_in[0] ^`
231			`crc_in[6] ^ current_crc[7] ^ current_crc[1] ^`
232			`crc_in[1] ^ crc_in[7];`
233			`next_crc[31] = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^`
234			`crc_in[7];`
235			`end // always`
236
237			`// assign tx_fcs = ~current_crc;`
238			`assign tx_fcs[0] = !current_crc[0];`
239			`assign tx_fcs[1] = !current_crc[1];`
240			`assign tx_fcs[2] = !current_crc[2];`
241			`assign tx_fcs[3] = !current_crc[3];`
242			`assign tx_fcs[4] = !current_crc[4];`
243			`assign tx_fcs[5] = !current_crc[5];`
244			`assign tx_fcs[6] = !current_crc[6];`
245			`assign tx_fcs[7] = !current_crc[7];`
246			`assign tx_fcs[8] = !current_crc[8];`
247			`assign tx_fcs[9] = !current_crc[9];`
248			`assign tx_fcs[10] = !current_crc[10];`
249			`assign tx_fcs[11] = !current_crc[11];`
250			`assign tx_fcs[12] = !current_crc[12];`
251			`assign tx_fcs[13] = !current_crc[13];`
252			`assign tx_fcs[14] = !current_crc[14];`
253			`assign tx_fcs[15] = !current_crc[15];`
254			`assign tx_fcs[16] = !current_crc[16];`
255			`assign tx_fcs[17] = !current_crc[17];`
256			`assign tx_fcs[18] = !current_crc[18];`
257			`assign tx_fcs[19] = !current_crc[19];`
258			`assign tx_fcs[20] = !current_crc[20];`
259			`assign tx_fcs[21] = !current_crc[21];`
260			`assign tx_fcs[22] = !current_crc[22];`
261			`assign tx_fcs[23] = !current_crc[23];`
262			`assign tx_fcs[24] = !current_crc[24];`
263			`assign tx_fcs[25] = !current_crc[25];`
264			`assign tx_fcs[26] = !current_crc[26];`
265			`assign tx_fcs[27] = !current_crc[27];`
266			`assign tx_fcs[28] = !current_crc[28];`
267			`assign tx_fcs[29] = !current_crc[29];`
268			`assign tx_fcs[30] = !current_crc[30];`
269			`assign tx_fcs[31] = !current_crc[31];`
270
271			`endmodule`