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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [crc32/] [g_tx_crc32.v] - Blame information for rev 57

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1 12 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Tubo 8051 cores MAC Interface Module                        ////
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////                                                              ////
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////  This file is part of the Turbo 8051 cores project           ////
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////  http://www.opencores.org/cores/turbo8051/                   ////
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////                                                              ////
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////  Description                                                 ////
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////  Turbo 8051 definitions.                                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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/***************************************************************
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  Description:
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  crc_32.v: This block contains the tx_crc32 generator.
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            CRC is generated on the tx data when gen_tx_crc asserted.
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            The 32-bit crc shift register is reset to all 1's when either
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            tx_reset_crc asserted
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 *********************************************************************/
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module g_tx_crc32 (
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              // List of outputs.
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              tx_fcs,
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              // List of inputs
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              gen_tx_crc,
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              tx_reset_crc,
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              tx_data,
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              sclk,
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              reset_n);
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  // defx[ine inputs and outputs.
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  input         gen_tx_crc;        // when asserted, crc is generated on the
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                                   // tx_data[3:0]. 
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  input         tx_reset_crc;      // when asserted, crc shift register is
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                                   // reset to all 1's. from link_phy_intfc.
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  input [7:0]    tx_data;           // trasnmit data.
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  input         sclk;              // serial clock from phy.
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  input         reset_n;             // global asynchronous reset.
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  output [31:0]  tx_fcs;       // 32-bit crc for tx_data. to link_phy_intfc.
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  // reg/wire declarations for primary outputs.
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  wire [31:0]    tx_fcs;
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  // define constants and parameters here.
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  // define local signals here.
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  wire [7:0]     crc_in;
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  wire          gen_crc;
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  wire[7:0]     tx_data_in;
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  wire          carry0,carry1,carry2,carry3;
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  wire          carry4,carry5,carry6,carry7;
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  reg [31:0]     current_crc, next_crc;
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  // code starts here.
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  assign tx_data_in = tx_data;
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  assign crc_in = tx_data_in;
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  assign gen_crc = gen_tx_crc;
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  // 32-bit crc shift register for crc calculation.
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  always @(posedge sclk or negedge reset_n)
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    begin
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      if (!reset_n)
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        begin
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          current_crc <= 32'hffffffff;
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        end
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      else
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        begin
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          if (tx_reset_crc )
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            begin
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              current_crc <= 32'hffffffff;
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            end
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          else if (gen_crc)  // generate crc 
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            begin
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              current_crc <= next_crc;
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            end // else: !if(tx_reset_crc )
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        end // else: !if(reset_n)
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    end // always @ (posedge sclk or negedge reset_n)
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  // combinational logic to generate next_crc
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  always @(current_crc or crc_in)
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    begin
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      next_crc[0]  = current_crc[8] ^ current_crc[2] ^ crc_in[2];
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            next_crc[1]  = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^
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                           current_crc[3] ^ crc_in[3];
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            next_crc[2]  = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^
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                           current_crc[1] ^ crc_in[1] ^ current_crc[4]  ^
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                                 crc_in[4];
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            next_crc[3]  = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^
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                           current_crc[2] ^ crc_in[2] ^ current_crc[5]  ^
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                                 crc_in[5];
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            next_crc[4]  = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^
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                           current_crc[3] ^ crc_in[3] ^ current_crc[6]  ^
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                                 current_crc[0] ^ crc_in[0] ^ crc_in[6];
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            next_crc[5]  = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^
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                           current_crc[4] ^ crc_in[4] ^ current_crc[7]  ^
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                                 current_crc[1] ^ crc_in[1] ^ crc_in[7];
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            next_crc[6]  = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^
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                           current_crc[5] ^ crc_in[5];
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            next_crc[7]  = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^
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                           current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                                 crc_in[6];
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            next_crc[8]  = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^
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                           current_crc[6]  ^ current_crc[0] ^ crc_in[0]  ^
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                                 crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
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                                 crc_in[1] ^ crc_in[7];
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            next_crc[9]  = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^
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                           current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
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                                 crc_in[7];
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            next_crc[10]  = current_crc[18] ^ current_crc[2] ^ crc_in[2];
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            next_crc[11]  = current_crc[19] ^ current_crc[3] ^ crc_in[3];
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            next_crc[12]  = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^
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                            current_crc[4]  ^ crc_in[4];
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            next_crc[13]  = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^
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                            current_crc[1]  ^ crc_in[1] ^ current_crc[5]  ^
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                                  crc_in[5];
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            next_crc[14]  = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^
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                            current_crc[1] ^ crc_in[1] ^ current_crc[2]  ^
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                            crc_in[2] ^ current_crc[6] ^ current_crc[0]  ^
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                                  crc_in[0] ^ crc_in[6];
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            next_crc[15]  = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^
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                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
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                                  crc_in[3] ^ current_crc[7] ^ current_crc[1]  ^
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                                  crc_in[1] ^ crc_in[7];
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            next_crc[16]  = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^
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                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
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                                  crc_in[3] ^ current_crc[4] ^ crc_in[4];
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            next_crc[17]  = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^
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                            current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
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                                  crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
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                                  current_crc[5] ^ crc_in[5];
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            next_crc[18]  = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^
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                            current_crc[2] ^ crc_in[2] ^ current_crc[4]  ^
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                                  crc_in[4] ^ current_crc[5] ^ crc_in[5]  ^
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                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                                  crc_in[6];
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            next_crc[19]  = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^
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                            current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
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                                  crc_in[3] ^ current_crc[5] ^ crc_in[5]  ^
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                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                                  crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
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                                  crc_in[1] ^ crc_in[7];
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            next_crc[20]  = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^
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                            current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
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                                  crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
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                                  current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                                  crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
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                                  crc_in[1] ^ crc_in[7];
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            next_crc[21]  = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^
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                      current_crc[2] ^ crc_in[2] ^ current_crc[4]  ^
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                      crc_in[4] ^ current_crc[5] ^ crc_in[5]  ^
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                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
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                      crc_in[7];
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            next_crc[22]  = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^
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                      current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
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                      crc_in[3] ^ current_crc[5] ^ crc_in[5]  ^
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                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                      crc_in[6];
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            next_crc[23]  = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^
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                      current_crc[1] ^ crc_in[1] ^ current_crc[3]  ^
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                      crc_in[3] ^ current_crc[4] ^ crc_in[4]  ^
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                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                      crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
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                      crc_in[1] ^ crc_in[7];
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            next_crc[24]  = current_crc[0] ^ crc_in[0] ^ current_crc[1]  ^
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                      crc_in[1] ^ current_crc[2] ^ crc_in[2]    ^
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                      current_crc[4] ^ crc_in[4] ^ current_crc[5]  ^
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                      crc_in[5] ^ current_crc[7] ^ current_crc[1]  ^
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                      crc_in[1] ^ crc_in[7];
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            next_crc[25]  = current_crc[1] ^ crc_in[1] ^ current_crc[2]  ^
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                            crc_in[2] ^ current_crc[3] ^ crc_in[3]    ^
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                      current_crc[5] ^ crc_in[5] ^ current_crc[6]  ^
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                      current_crc[0]  ^ crc_in[0] ^ crc_in[6];
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            next_crc[26]  = current_crc[2] ^ crc_in[2] ^ current_crc[3]  ^
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                      crc_in[3] ^ current_crc[4] ^ crc_in[4]    ^
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                      current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                      crc_in[6]  ^ current_crc[7] ^ current_crc[1] ^
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                      crc_in[1]  ^ crc_in[7];
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            next_crc[27]  = current_crc[3] ^ crc_in[3] ^ current_crc[4]  ^
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                      crc_in[4] ^ current_crc[5] ^ crc_in[5]    ^
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                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
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                      crc_in[7];
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            next_crc[28]  = current_crc[4] ^crc_in[4] ^ current_crc[5]   ^
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                      crc_in[5] ^ current_crc[6] ^ current_crc[0]  ^
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                      crc_in[0] ^ crc_in[6];
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            next_crc[29]  = current_crc[5] ^ crc_in[5] ^ current_crc[6]  ^
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                      current_crc[0] ^ crc_in[0] ^ crc_in[6]    ^
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                      current_crc[7] ^ current_crc[1] ^ crc_in[1]  ^
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                      crc_in[7];
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            next_crc[30]  = current_crc[6] ^ current_crc[0] ^ crc_in[0]  ^
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                      crc_in[6] ^ current_crc[7] ^ current_crc[1]  ^
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                      crc_in[1] ^ crc_in[7];
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            next_crc[31]  = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
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                      crc_in[7];
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    end   // always
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//  assign tx_fcs = ~current_crc;
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  assign tx_fcs[0] = !current_crc[0];
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  assign tx_fcs[1] = !current_crc[1];
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  assign tx_fcs[2] = !current_crc[2];
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  assign tx_fcs[3] = !current_crc[3];
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  assign tx_fcs[4] = !current_crc[4];
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  assign tx_fcs[5] = !current_crc[5];
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  assign tx_fcs[6] = !current_crc[6];
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  assign tx_fcs[7] = !current_crc[7];
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  assign tx_fcs[8] = !current_crc[8];
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  assign tx_fcs[9] = !current_crc[9];
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  assign tx_fcs[10] = !current_crc[10];
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  assign tx_fcs[11] = !current_crc[11];
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  assign tx_fcs[12] = !current_crc[12];
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  assign tx_fcs[13] = !current_crc[13];
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  assign tx_fcs[14] = !current_crc[14];
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  assign tx_fcs[15] = !current_crc[15];
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  assign tx_fcs[16] = !current_crc[16];
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  assign tx_fcs[17] = !current_crc[17];
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  assign tx_fcs[18] = !current_crc[18];
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  assign tx_fcs[19] = !current_crc[19];
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  assign tx_fcs[20] = !current_crc[20];
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  assign tx_fcs[21] = !current_crc[21];
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  assign tx_fcs[22] = !current_crc[22];
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  assign tx_fcs[23] = !current_crc[23];
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  assign tx_fcs[24] = !current_crc[24];
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  assign tx_fcs[25] = !current_crc[25];
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  assign tx_fcs[26] = !current_crc[26];
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  assign tx_fcs[27] = !current_crc[27];
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  assign tx_fcs[28] = !current_crc[28];
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  assign tx_fcs[29] = !current_crc[29];
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  assign tx_fcs[30] = !current_crc[30];
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  assign tx_fcs[31] = !current_crc[31];
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endmodule

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