Subversion Repositories turbo8051

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Tubo 8051 cores MAC Interface Module                        ////

////                                                              ////

////  This file is part of the Turbo 8051 cores project           ////

////  http://www.opencores.org/cores/turbo8051/                   ////

////                                                              ////

////  Description                                                 ////

////  Turbo 8051 definitions.                                     ////

////                                                              ////

////  To Do:                                                      ////

////    nothing                                                   ////

////                                                              ////

////  Author(s):                                                  ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////                                                              ////

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////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

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/***************************************************************

  Description:

  byte_reg.v: instantiates 32 registers to make a quad

              This enables maintaining timing on blocks

              in check

***********************************************************************/

module  half_dup_byte_reg(

  //List of Inputs

  we,

  data_in,

  reset_n,

  clk,

  //List of Outputs

  data_out

);

  input [7:0] we;

  input [7:0]    data_in;

  input         reset_n;

  input         clk;

  output [7:0]   data_out;

  generic_register #(8,0) u_reg (

    .we          (we),

    .clk         (clk),

    .reset_n     (reset_n),

    .data_in     (data_in),

    .data_out    (data_out)

    );

endmodule