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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [mac/] [g_deferral.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores MAC Interface Module                        ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
 
/***************************************************************
  Description:
  deferral.v : This block performs the deferral algorithm for
               half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2
               This block also implements the optional two part deferral
               mechanism.
***********************************************************************/
 
module g_deferral (
                 df2tx_dfl_dn,
                 cf2df_dfl_single,
                 phy_tx_en,
                 phy_tx_er,
                 tx_clk,
                 app_reset_n);
 
 
  input [7:0] cf2df_dfl_single;           //program with 9.6 ms
  input        phy_tx_en;                 //TX frame is done, wait for IPG
                                          //used in FULL duplex
  input        phy_tx_er;                 //TX Error 
  input        tx_clk;              //MII provided tx_clk
  input        app_reset_n;
 
  output       df2tx_dfl_dn;              //when active hold the TX, else
                                    //TX can send preamble  
 
  wire         df2tx_dfl_dn;
 
  parameter    dfl_idle_st =        6'b000000;
  parameter    dfl_dfl_st =         6'b000010;
  parameter    dfl_full_tx_dn_st =  6'b010000;
  parameter    dfl_wipg_st =        6'b100000;
 
  reg [5:0]    curr_dfl_st, nxt_dfl_st;
  reg          dfl_dn;
  reg          strt_dfl;
  reg [7:0]   dfl_cntr;
 
  reg         phy_tx_en_d;
 
  wire        was_xmitted;
 
  assign df2tx_dfl_dn = dfl_dn;
  /*****************************************************************
   * Synchronous process for the FSM to enable and disable TX on
   * receive activity
   *****************************************************************/
  always @(posedge tx_clk or negedge app_reset_n)
    begin
      if (!app_reset_n)
        curr_dfl_st <= dfl_idle_st;
      else
        curr_dfl_st <= nxt_dfl_st;
    end // always @ (posedge tx_clk or negedge app_reset_n)
 
  /*****************************************************************
   * comb        process for the FSM to enable and disable TX on
   * receive activity
   *****************************************************************/
  always @(curr_dfl_st or dfl_cntr
           or phy_tx_en or phy_tx_er or was_xmitted)
    begin
      strt_dfl = 0;
      dfl_dn = 0;
      nxt_dfl_st = curr_dfl_st;
 
      case (curr_dfl_st)
        dfl_idle_st :
          begin
            dfl_dn = 1;
            if (phy_tx_en)
              begin
                dfl_dn = 0;
                nxt_dfl_st = dfl_full_tx_dn_st;
              end // if (phy_tx_en)
            else
              nxt_dfl_st = dfl_idle_st;
          end // case: dfl_idle_st
 
        dfl_full_tx_dn_st :
          begin
            // full duplex mode, wait till the current tx
            // frame is transmitted and wait for IPG time,
            // no need to wait for two part defferal
            if (!phy_tx_en && !phy_tx_er)
              begin
                strt_dfl = 1;
                nxt_dfl_st = dfl_wipg_st;
              end // if (!phy_tx_en)
            else
              nxt_dfl_st = dfl_full_tx_dn_st;
          end // case: dfl_full_tx_dn_st
 
        dfl_wipg_st :
          begin
            // This state is reached when there is no transmit
            // in progress. In this state IPG counter should checked
            // and upon its expiry indicate deferral done
            // to tx_fsm block
            if (dfl_cntr == 8'd0)
              begin
                dfl_dn = 1;
                nxt_dfl_st = dfl_idle_st;
              end
            else
              nxt_dfl_st = dfl_wipg_st;
          end // case: dfl_wipg_st
 
        default :
          begin
            nxt_dfl_st = dfl_idle_st;
          end
      endcase // case (curr_dfl_st)
    end // always @ (curr_dfl_st )
 
  //counter for the single phase deferral scheme
  always @(posedge tx_clk or negedge app_reset_n)
    begin
      if (!app_reset_n)
        dfl_cntr <= 8'd0;
      else
        begin
          if (strt_dfl)
            begin
               dfl_cntr <= cf2df_dfl_single;
            end
          else
            dfl_cntr <= dfl_cntr - 1;
        end // else: !if(app_reset_n)
    end // always @ (posedge tx_clk or negedge app_reset_n)
 
 
   // Mandar
   // Detect Packet end
   assign was_xmitted = (phy_tx_en_d == 1'b1 && phy_tx_en == 1'b0) ? 1'b1 : 1'b0;
 
 
   always @(posedge tx_clk or negedge app_reset_n)
     begin
       if (!app_reset_n)
          phy_tx_en_d <= 1'b0;
       else
          phy_tx_en_d <= phy_tx_en;
     end // always @ (posedge tx_clk or negedge app_reset_n)
 
 
 
endmodule // deferral
 
 
 
 

Line No.	Rev	Author	Line
1	12	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tubo 8051 cores MAC Interface Module ////`
4			`//// ////`
5			`//// This file is part of the Turbo 8051 cores project ////`
6			`//// http://www.opencores.org/cores/turbo8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Turbo 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			//`timescale 1ns/100ps
44
45			`/***************************************************************`
46			`Description:`
47			`deferral.v : This block performs the deferral algorithm for`
48			`half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2`
49			`This block also implements the optional two part deferral`
50			`mechanism.`
51			`***********************************************************************/`
52
53			`module g_deferral (`
54			`df2tx_dfl_dn,`
55			`cf2df_dfl_single,`
56			`phy_tx_en,`
57			`phy_tx_er,`
58			`tx_clk,`
59			`app_reset_n);`
60
61
62			`input [7:0] cf2df_dfl_single; //program with 9.6 ms`
63			`input phy_tx_en; //TX frame is done, wait for IPG`
64			`//used in FULL duplex`
65			`input phy_tx_er; //TX Error`
66			`input tx_clk; //MII provided tx_clk`
67			`input app_reset_n;`
68
69			`output df2tx_dfl_dn; //when active hold the TX, else`
70			`//TX can send preamble`
71
72			`wire df2tx_dfl_dn;`
73
74			`parameter dfl_idle_st = 6'b000000;`
75			`parameter dfl_dfl_st = 6'b000010;`
76			`parameter dfl_full_tx_dn_st = 6'b010000;`
77			`parameter dfl_wipg_st = 6'b100000;`
78
79			`reg [5:0] curr_dfl_st, nxt_dfl_st;`
80			`reg dfl_dn;`
81			`reg strt_dfl;`
82			`reg [7:0] dfl_cntr;`
83
84			`reg phy_tx_en_d;`
85
86			`wire was_xmitted;`
87
88			`assign df2tx_dfl_dn = dfl_dn;`
89			`/*****************************************************************`
90			`* Synchronous process for the FSM to enable and disable TX on`
91			`* receive activity`
92			`*****************************************************************/`
93			`always @(posedge tx_clk or negedge app_reset_n)`
94			`begin`
95			`if (!app_reset_n)`
96			`curr_dfl_st <= dfl_idle_st;`
97			`else`
98			`curr_dfl_st <= nxt_dfl_st;`
99			`end // always @ (posedge tx_clk or negedge app_reset_n)`
100
101			`/*****************************************************************`
102			`* comb process for the FSM to enable and disable TX on`
103			`* receive activity`
104			`*****************************************************************/`
105			`always @(curr_dfl_st or dfl_cntr`
106			`or phy_tx_en or phy_tx_er or was_xmitted)`
107			`begin`
108			`strt_dfl = 0;`
109			`dfl_dn = 0;`
110			`nxt_dfl_st = curr_dfl_st;`
111
112			`case (curr_dfl_st)`
113			`dfl_idle_st :`
114			`begin`
115			`dfl_dn = 1;`
116			`if (phy_tx_en)`
117			`begin`
118			`dfl_dn = 0;`
119			`nxt_dfl_st = dfl_full_tx_dn_st;`
120			`end // if (phy_tx_en)`
121			`else`
122			`nxt_dfl_st = dfl_idle_st;`
123			`end // case: dfl_idle_st`
124
125			`dfl_full_tx_dn_st :`
126			`begin`
127			`// full duplex mode, wait till the current tx`
128			`// frame is transmitted and wait for IPG time,`
129			`// no need to wait for two part defferal`
130			`if (!phy_tx_en && !phy_tx_er)`
131			`begin`
132			`strt_dfl = 1;`
133			`nxt_dfl_st = dfl_wipg_st;`
134			`end // if (!phy_tx_en)`
135			`else`
136			`nxt_dfl_st = dfl_full_tx_dn_st;`
137			`end // case: dfl_full_tx_dn_st`
138
139			`dfl_wipg_st :`
140			`begin`
141			`// This state is reached when there is no transmit`
142			`// in progress. In this state IPG counter should checked`
143			`// and upon its expiry indicate deferral done`
144			`// to tx_fsm block`
145			`if (dfl_cntr == 8'd0)`
146			`begin`
147			`dfl_dn = 1;`
148			`nxt_dfl_st = dfl_idle_st;`
149			`end`
150			`else`
151			`nxt_dfl_st = dfl_wipg_st;`
152			`end // case: dfl_wipg_st`
153
154			`default :`
155			`begin`
156			`nxt_dfl_st = dfl_idle_st;`
157			`end`
158			`endcase // case (curr_dfl_st)`
159			`end // always @ (curr_dfl_st )`
160
161			`//counter for the single phase deferral scheme`
162			`always @(posedge tx_clk or negedge app_reset_n)`
163			`begin`
164			`if (!app_reset_n)`
165			`dfl_cntr <= 8'd0;`
166			`else`
167			`begin`
168			`if (strt_dfl)`
169			`begin`
170			`dfl_cntr <= cf2df_dfl_single;`
171			`end`
172			`else`
173			`dfl_cntr <= dfl_cntr - 1;`
174			`end // else: !if(app_reset_n)`
175			`end // always @ (posedge tx_clk or negedge app_reset_n)`
176
177
178			`// Mandar`
179			`// Detect Packet end`
180			`assign was_xmitted = (phy_tx_en_d == 1'b1 && phy_tx_en == 1'b0) ? 1'b1 : 1'b0;`
181
182
183			`always @(posedge tx_clk or negedge app_reset_n)`
184			`begin`
185			`if (!app_reset_n)`
186			`phy_tx_en_d <= 1'b0;`
187			`else`
188			`phy_tx_en_d <= phy_tx_en;`
189			`end // always @ (posedge tx_clk or negedge app_reset_n)`
190
191
192
193			`endmodule // deferral`
194
195
196
197

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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [mac/] [g_deferral.v] - Blame information for rev 12