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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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/***************************************************************
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Description:
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deferral.v : This block performs the deferral algorithm for
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half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2
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This block also implements the optional two part deferral
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mechanism.
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***********************************************************************/
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module g_deferral_rx (
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rx_dfl_dn,
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dfl_single,
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rx_dv,
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rx_clk,
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reset_n);
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input [7:0] dfl_single; //program with 9.6 ms
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input rx_dv; //TX frame is done, wait for IPG
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//used in FULL duplex
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input rx_clk; //MII provided rx_clk
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input reset_n;
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output rx_dfl_dn; //when active hold the TX, else
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//TX can send preamble
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parameter dfl_idle_st = 6'b000000;
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parameter dfl_dfl_st = 6'b000010;
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parameter dfl_full_tx_dn_st = 6'b010000;
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parameter dfl_wipg_st = 6'b100000;
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reg [5:0] curr_dfl_st, nxt_dfl_st;
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reg rx_dfl_dn;
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reg strt_dfl;
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reg [8:0] fst_dfl_cntr;
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reg [8:0] dfl_cntr;
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reg [8:0] scnd_dfl_cntr;
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/*****************************************************************
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* Synchronous process for the FSM to enable and disable TX on
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* receive activity
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*****************************************************************/
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always @(posedge rx_clk or negedge reset_n)
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begin
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if (!reset_n)
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curr_dfl_st <= dfl_idle_st;
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else
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curr_dfl_st <= nxt_dfl_st;
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end // always @ (posedge rx_clk or negedge reset_n)
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/*****************************************************************
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* comb process for the FSM to enable and disable TX on
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* receive activity
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*****************************************************************/
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always @(curr_dfl_st or dfl_cntr or rx_dv)
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begin
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strt_dfl = 0;
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rx_dfl_dn = 0;
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nxt_dfl_st = curr_dfl_st;
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case (curr_dfl_st)
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dfl_idle_st :
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begin
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rx_dfl_dn = 1;
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if (rx_dv)
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begin
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rx_dfl_dn = 0;
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nxt_dfl_st = dfl_full_tx_dn_st;
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end // if (rx_dv)
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else
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nxt_dfl_st = dfl_idle_st;
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end // case: dfl_idle_st
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dfl_full_tx_dn_st :
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begin
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// full duplex mode, wait till the current tx
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// frame is transmitted and wait for IPG time,
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// no need to wait for two part defferal
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if (!rx_dv)
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begin
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strt_dfl = 1;
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nxt_dfl_st = dfl_wipg_st;
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end // if (!rx_dv)
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else
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nxt_dfl_st = dfl_full_tx_dn_st;
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end // case: dfl_full_tx_dn_st
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dfl_wipg_st :
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begin
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// This state is reached when there is no transmit
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// in progress. In this state IPG counter should checked
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// and upon its expiry indicate deferral done
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// to tx_fsm block
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if (dfl_cntr == 9'd0)
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begin
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rx_dfl_dn = 1;
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nxt_dfl_st = dfl_idle_st;
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end
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else
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nxt_dfl_st = dfl_wipg_st;
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end // case: dfl_wipg_st
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dfl_dfl_st :
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//wait in this state till deferral time is done
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//if CRS is active before the deferral time
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//restart the deferral process again
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begin
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begin
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if (dfl_cntr == 9'd0)
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begin
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rx_dfl_dn = 1;
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nxt_dfl_st = dfl_idle_st;
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end
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else
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nxt_dfl_st = dfl_dfl_st;
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end //
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end // case: dfl_dfl_st
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default :
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begin
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nxt_dfl_st = dfl_idle_st;
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end
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endcase // case (curr_dfl_st)
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end // always @ (curr_dfl_st )
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//counter for the single phase deferral scheme
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always @(posedge rx_clk or negedge reset_n)
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begin
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if (!reset_n)
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dfl_cntr <= 9'd0;
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else
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begin
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if (strt_dfl)
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begin
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dfl_cntr[7:0] <= dfl_single;
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dfl_cntr[8] <= 0;
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end
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else
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dfl_cntr <= dfl_cntr - 1;
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end // else: !if(reset_n)
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end // always @ (posedge rx_clk or negedge reset_n)
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endmodule // deferral
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