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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [mac/] [g_deferral_rx.v] - Blame information for rev 76

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores MAC Interface Module                        ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Mar 2, 2011                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
/***************************************************************
  Description:
  deferral.v : This block performs the deferral algorithm for
               half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2
               This block also implements the optional two part deferral
               mechanism.
***********************************************************************/
 
module g_deferral_rx (
                 rx_dfl_dn,
                 dfl_single,
                 rx_dv,
                 rx_clk,
                 reset_n);
 
 
  input [7:0] dfl_single;           //program with 9.6 ms
  input        rx_dv;               //TX frame is done, wait for IPG
                                    //used in FULL duplex
  input        rx_clk;              //MII provided rx_clk
  input        reset_n;
 
  output       rx_dfl_dn;              //when active hold the TX, else
                                    //TX can send preamble  
 
  parameter    dfl_idle_st =        6'b000000;
  parameter    dfl_dfl_st =         6'b000010;
  parameter    dfl_full_tx_dn_st =  6'b010000;
  parameter    dfl_wipg_st =        6'b100000;
 
  reg [5:0]    curr_dfl_st, nxt_dfl_st;
  reg          rx_dfl_dn;
  reg          strt_dfl;
  reg [8:0]   fst_dfl_cntr;
  reg [8:0]   dfl_cntr;
  reg [8:0]   scnd_dfl_cntr;
 
  /*****************************************************************
   * Synchronous process for the FSM to enable and disable TX on
   * receive activity
   *****************************************************************/
  always @(posedge rx_clk or negedge reset_n)
    begin
      if (!reset_n)
        curr_dfl_st <= dfl_idle_st;
      else
        curr_dfl_st <= nxt_dfl_st;
    end // always @ (posedge rx_clk or negedge reset_n)
 
  /*****************************************************************
   * comb        process for the FSM to enable and disable TX on
   * receive activity
   *****************************************************************/
  always @(curr_dfl_st or dfl_cntr or rx_dv)
    begin
      strt_dfl = 0;
      rx_dfl_dn = 0;
      nxt_dfl_st = curr_dfl_st;
 
      case (curr_dfl_st)
        dfl_idle_st :
          begin
            rx_dfl_dn = 1;
            if (rx_dv)
              begin
                rx_dfl_dn = 0;
                nxt_dfl_st = dfl_full_tx_dn_st;
              end // if (rx_dv)
            else
              nxt_dfl_st = dfl_idle_st;
          end // case: dfl_idle_st
 
        dfl_full_tx_dn_st :
          begin
            // full duplex mode, wait till the current tx
            // frame is transmitted and wait for IPG time,
            // no need to wait for two part defferal
            if (!rx_dv)
              begin
                strt_dfl = 1;
                nxt_dfl_st = dfl_wipg_st;
              end // if (!rx_dv)
            else
              nxt_dfl_st = dfl_full_tx_dn_st;
          end // case: dfl_full_tx_dn_st
 
        dfl_wipg_st :
          begin
            // This state is reached when there is no transmit
            // in progress. In this state IPG counter should checked
            // and upon its expiry indicate deferral done
            // to tx_fsm block
            if (dfl_cntr == 9'd0)
              begin
                rx_dfl_dn = 1;
                nxt_dfl_st = dfl_idle_st;
              end
            else
              nxt_dfl_st = dfl_wipg_st;
          end // case: dfl_wipg_st
 
        dfl_dfl_st :
          //wait in this state till deferral time is done
          //if CRS is active before the deferral time
          //restart the deferral process again
          begin
              begin
                if (dfl_cntr == 9'd0)
                  begin
                      rx_dfl_dn = 1;
                      nxt_dfl_st = dfl_idle_st;
                  end
                else
                  nxt_dfl_st = dfl_dfl_st;
              end // 
          end // case: dfl_dfl_st
 
        default :
          begin
            nxt_dfl_st = dfl_idle_st;
          end
      endcase // case (curr_dfl_st)
    end // always @ (curr_dfl_st  )
 
  //counter for the single phase deferral scheme
  always @(posedge rx_clk or negedge reset_n)
    begin
      if (!reset_n)
        dfl_cntr <= 9'd0;
      else
        begin
          if (strt_dfl)
            begin
              dfl_cntr[7:0] <= dfl_single;
              dfl_cntr[8] <= 0;
            end
          else
            dfl_cntr <= dfl_cntr - 1;
        end // else: !if(reset_n)
    end // always @ (posedge rx_clk or negedge reset_n)
 
endmodule // deferral
 
 
 
 

Line No.	Rev	Author	Line
1	12	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tubo 8051 cores MAC Interface Module ////`
4			`//// ////`
5			`//// This file is part of the Turbo 8051 cores project ////`
6			`//// http://www.opencores.org/cores/turbo8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Turbo 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17	76	dinesha	`//// Revision : Mar 2, 2011 ////`
18			`//// ////`
19	12	dinesha	`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45
46			`/***************************************************************`
47			`Description:`
48			`deferral.v : This block performs the deferral algorithm for`
49			`half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2`
50			`This block also implements the optional two part deferral`
51			`mechanism.`
52			`***********************************************************************/`
53
54			`module g_deferral_rx (`
55			`rx_dfl_dn,`
56			`dfl_single,`
57			`rx_dv,`
58			`rx_clk,`
59			`reset_n);`
60
61
62			`input [7:0] dfl_single; //program with 9.6 ms`
63			`input rx_dv; //TX frame is done, wait for IPG`
64			`//used in FULL duplex`
65			`input rx_clk; //MII provided rx_clk`
66			`input reset_n;`
67
68			`output rx_dfl_dn; //when active hold the TX, else`
69			`//TX can send preamble`
70
71			`parameter dfl_idle_st = 6'b000000;`
72			`parameter dfl_dfl_st = 6'b000010;`
73			`parameter dfl_full_tx_dn_st = 6'b010000;`
74			`parameter dfl_wipg_st = 6'b100000;`
75
76			`reg [5:0] curr_dfl_st, nxt_dfl_st;`
77			`reg rx_dfl_dn;`
78			`reg strt_dfl;`
79			`reg [8:0] fst_dfl_cntr;`
80			`reg [8:0] dfl_cntr;`
81			`reg [8:0] scnd_dfl_cntr;`
82
83			`/*****************************************************************`
84			`* Synchronous process for the FSM to enable and disable TX on`
85			`* receive activity`
86			`*****************************************************************/`
87			`always @(posedge rx_clk or negedge reset_n)`
88			`begin`
89			`if (!reset_n)`
90			`curr_dfl_st <= dfl_idle_st;`
91			`else`
92			`curr_dfl_st <= nxt_dfl_st;`
93			`end // always @ (posedge rx_clk or negedge reset_n)`
94
95			`/*****************************************************************`
96			`* comb process for the FSM to enable and disable TX on`
97			`* receive activity`
98			`*****************************************************************/`
99			`always @(curr_dfl_st or dfl_cntr or rx_dv)`
100			`begin`
101			`strt_dfl = 0;`
102			`rx_dfl_dn = 0;`
103			`nxt_dfl_st = curr_dfl_st;`
104
105			`case (curr_dfl_st)`
106			`dfl_idle_st :`
107			`begin`
108			`rx_dfl_dn = 1;`
109			`if (rx_dv)`
110			`begin`
111			`rx_dfl_dn = 0;`
112			`nxt_dfl_st = dfl_full_tx_dn_st;`
113			`end // if (rx_dv)`
114			`else`
115			`nxt_dfl_st = dfl_idle_st;`
116			`end // case: dfl_idle_st`
117
118			`dfl_full_tx_dn_st :`
119			`begin`
120			`// full duplex mode, wait till the current tx`
121			`// frame is transmitted and wait for IPG time,`
122			`// no need to wait for two part defferal`
123			`if (!rx_dv)`
124			`begin`
125			`strt_dfl = 1;`
126			`nxt_dfl_st = dfl_wipg_st;`
127			`end // if (!rx_dv)`
128			`else`
129			`nxt_dfl_st = dfl_full_tx_dn_st;`
130			`end // case: dfl_full_tx_dn_st`
131
132			`dfl_wipg_st :`
133			`begin`
134			`// This state is reached when there is no transmit`
135			`// in progress. In this state IPG counter should checked`
136			`// and upon its expiry indicate deferral done`
137			`// to tx_fsm block`
138			`if (dfl_cntr == 9'd0)`
139			`begin`
140			`rx_dfl_dn = 1;`
141			`nxt_dfl_st = dfl_idle_st;`
142			`end`
143			`else`
144			`nxt_dfl_st = dfl_wipg_st;`
145			`end // case: dfl_wipg_st`
146
147			`dfl_dfl_st :`
148			`//wait in this state till deferral time is done`
149			`//if CRS is active before the deferral time`
150			`//restart the deferral process again`
151			`begin`
152			`begin`
153			`if (dfl_cntr == 9'd0)`
154			`begin`
155			`rx_dfl_dn = 1;`
156			`nxt_dfl_st = dfl_idle_st;`
157			`end`
158			`else`
159			`nxt_dfl_st = dfl_dfl_st;`
160			`end //`
161			`end // case: dfl_dfl_st`
162
163			`default :`
164			`begin`
165			`nxt_dfl_st = dfl_idle_st;`
166			`end`
167			`endcase // case (curr_dfl_st)`
168			`end // always @ (curr_dfl_st )`
169
170			`//counter for the single phase deferral scheme`
171			`always @(posedge rx_clk or negedge reset_n)`
172			`begin`
173			`if (!reset_n)`
174			`dfl_cntr <= 9'd0;`
175			`else`
176			`begin`
177			`if (strt_dfl)`
178			`begin`
179			`dfl_cntr[7:0] <= dfl_single;`
180			`dfl_cntr[8] <= 0;`
181			`end`
182			`else`
183			`dfl_cntr <= dfl_cntr - 1;`
184			`end // else: !if(reset_n)`
185			`end // always @ (posedge rx_clk or negedge reset_n)`
186
187			`endmodule // deferral`
188
189
190
191

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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [mac/] [g_deferral_rx.v] - Blame information for rev 76