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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//`timescale 1ns/100ps
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/***************************************************************
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Description:
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mii_intf.v: This verilog file is reduced mii interface for ethenet
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The transmit state machine generates a condition to indicate
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start transmit. This is done using strt_preamble. The transmit
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state machine upon detecting strt_preamble generates pre-amble
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and start of frame de-limiter and then starts accepting the data
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from the transmit block by asserting the transmit nibble ack.
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***************************************************************/
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/************** MODULE DECLARATION ****************************/
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module g_mii_intf(
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// Data and Control Signals to tx_fsm and rx_fsm
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mi2rx_strt_rcv,
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mi2rx_rcv_vld,
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mi2rx_rx_byte,
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mi2rx_end_rcv,
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mi2rx_extend,
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mi2rx_frame_err,
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mi2rx_end_frame,
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mi2rx_crs,
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mi2tx_byte_ack,
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mi2tx_slot_vld,
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cfg_uni_mac_mode_change,
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// Phy Signals
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phy_tx_en,
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phy_tx_er,
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phy_txd,
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phy_tx_clk,
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phy_rx_clk,
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tx_reset_n,
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rx_reset_n,
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phy_rx_er,
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phy_rx_dv,
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phy_rxd,
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phy_crs,
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// rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
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rx_sts_rx_er_reg,
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// Reset signal
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app_reset_n,
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// Signals from Config Management
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cf2mi_loopback_en,
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cf2mi_rmii_en,
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cf_mac_mode,
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cf_chk_rx_dfl,
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cf_silent_mode,
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// Signal from Application to transmit JAM
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df2rx_dfl_dn,
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// Inputs from Transmit FSM
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tx2mi_strt_preamble,
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tx2mi_end_transmit,
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tx2mi_tx_byte,
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tx_ch_en
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);
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parameter NO_GMII_PREAMBLE = 5'b00111;
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parameter NO_MII_PREAMBLE = 5'b01111;
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parameter NO_RMII_PREAMBLE = 5'b11111;
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parameter GMII_JAM_COUNT = 5'b0011;
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parameter MII_JAM_COUNT = 5'b0111;
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parameter RMII_JAM_COUNT = 5'b1111;
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/******* INPUT & OUTPUT DECLARATIONS *************************/
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output mi2rx_strt_rcv; // This is generated by the MII block to indicate start
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// of receive data.
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output mi2rx_rcv_vld; // This signal is asserted by MII on reception of valid
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// bytes to indicate to the RX block to accept data from PHY
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output[7:0] mi2rx_rx_byte; // This the receive data from the PHY gathered as bytes
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output mi2rx_end_rcv; // This signal is asserted with the last data assembled
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output mi2rx_extend; // This signal is asserted during carrier extension (Receive)
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output mi2rx_frame_err; // This signal is asserted during Dibit Error (In RMII Mode)
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// or Nibble Error in (MII Mode)
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output mi2rx_end_frame; // End of Frame
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output mi2rx_crs; // CRS signal in rx_clk domain
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output mi2tx_byte_ack; // MII block acknowledges a byte during transmit
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output mi2tx_slot_vld; // MII block acknowledges valid slot during transmit // mfilardo
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output phy_tx_en; // Enable data on TX
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output phy_tx_er; // Transmit Error (Used in Carrier Extension in 1000 Mode)
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output[7:0] phy_txd; // Transmit data on the line
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input phy_tx_clk; // Transmit Clock in 10/100 Mb/s
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output rx_sts_rx_er_reg; // rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
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input app_reset_n; // reset from the application interface
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input phy_rx_clk; // Receive Clock in 10/100/1000 Mb/s
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input phy_rx_er; // Receive Error. Used in Carrier Extension in 1000 Mode
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input phy_rx_dv; // Receive Data Valid from the PHY
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input[7:0] phy_rxd; // Receive Data
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input phy_crs; // Carrier Sense from the line
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input tx_reset_n;
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input rx_reset_n;
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input cf2mi_loopback_en; // loop back enable
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input cf2mi_rmii_en; // RMII Mode
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input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
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input cf_chk_rx_dfl; // Check for Deferal
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input cf_silent_mode; // PHY Inactive
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input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
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input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
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// preamble on the line
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input tx2mi_end_transmit; // This is provided by the TX block to
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// indicate end of transmit
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input[7:0] tx2mi_tx_byte; // 8 bits of data from Tx block
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input tx_ch_en; // Transmitt Enable
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input cfg_uni_mac_mode_change;
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/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
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reg phy_tx_en;
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reg mi2tx_byte_ack;
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reg mi2tx_slot_vld;
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reg [7:0] phy_txd;
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wire [7:0] mi2rx_rx_byte;
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reg [7:0] mi2rx_rx_byte_in;
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reg mi2rx_extend;
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reg mi2rx_extend_err;
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reg mi2rx_strt_rcv;
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reg mi2rx_end_rcv;
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reg mi2rx_rcv_vld;
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reg mi2rx_frame_err;
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/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
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reg [4:0] tx_preamble_cnt_val;
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reg strt_rcv_in;
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reg end_rcv_in;
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reg rx_dv_in;
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reg rx_er_in;
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reg rcv_valid_in;
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reg [7:0] rxd_in;
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parameter mii_rx_idle_st = 3'd0, mii_rx_pre_st = 3'd1,
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mii_rx_byte_st = 3'd2, mii_rx_end_st = 3'd3,
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mii_rx_dibit_st = 3'd4, mii_rx_nibble_st = 3'd5;
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reg [2:0] mii_rx_nxt_st;
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reg [2:0] mii_rx_cur_st;
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parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
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mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
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dinesha |
mii_tx_nibble_st = 4'd5,
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dinesha |
mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
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mii_tx_dibit_end_st = 4'd8;
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reg [3:0] mii_tx_cur_st;
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reg [3:0] mii_tx_nxt_st;
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wire receive_detect;
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wire pre_condition;
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wire sfd_condition;
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wire tx_en;
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wire tx_er;
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wire [7:0] txd;
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wire byte_boundary_rx, byte_boundary_tx;
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reg tx_en_in;
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reg tx_err_in;
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reg tx_ext_in;
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reg tx_pre_in;
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reg tx_sfd_in;
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reg tx_xfr_ack_in;
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reg inc_preamble_cntr;
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reg rst_preamble_cntr;
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reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
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reg rx_dv;
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reg rx_er;
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reg rcv_err_in;
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reg mi2rx_end_frame_in;
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reg [1:0] tx_dibit_in;
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reg mi2rx_extend_in, mi2rx_extend_err_in, mi2rx_end_frame;
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reg crs_in;
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reg phy_tx_er;
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wire dibit_check_rx, dibit_check_tx;
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wire nibble_check_rx, nibble_check_tx;
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wire pre_condition_gmii, pre_condition_mii, pre_condition_rmii;
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wire sfd_condition_gmii, sfd_condition_mii, sfd_condition_rmii;
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wire [3:0] tx_nibble_in;
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reg [7:0] rxd;
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wire receive_detect_pulse;
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reg d_receive_detect;
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reg lb_tx_en, lb_tx_er;
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reg rx_dv_del;
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reg [1:0] rxd_del;
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reg rx_dfl_dn;
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reg rx_dfl_dn_reg;
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/******** SEQUENTIAL LOGIC **********************************/
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// This logic generates appropriate receive data valid
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// in case of loop back
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always @(tx_en or phy_rxd or txd or phy_rx_dv or tx_er or phy_crs
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or cf2mi_loopback_en or phy_tx_en or phy_rx_er or
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cf2mi_rmii_en or cf_mac_mode)
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begin
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if(cf2mi_loopback_en)
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begin
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rx_dv_in = tx_en;
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rx_er_in = tx_er;
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rxd_in = txd;
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crs_in = (tx_en | tx_er) && cf_mac_mode;
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end // if (mii_loopback_en)
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else
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begin
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rx_dv_in = phy_rx_dv ;
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rx_er_in = phy_rx_er;
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rxd_in = phy_rxd;
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// *** NOTE ****
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// phy_crs should be a combination of crs and tx_en
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// In Full Duplex tx_en determines deferral in half duplex
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// crs determines deferral
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crs_in = (tx_en | tx_er);
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end // else: !if(mii_loopback_en)
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end
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// Following state machine is to detect start preamble and
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// transmit preamble and sfd and then the data.
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// This state machine also generates acknowledge to TX block
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// to allow the TX block to update its byte pointers
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always @(posedge phy_tx_clk or negedge tx_reset_n)
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begin
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if(!tx_reset_n)
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begin
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mii_tx_cur_st <= mii_tx_idle_st;
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end
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else if (tx_ch_en)
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begin
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mii_tx_cur_st <= mii_tx_nxt_st;
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end
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else
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begin
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mii_tx_cur_st <= mii_tx_idle_st;
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end
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end
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always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
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or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
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37 |
dinesha |
or tx_xfr_cnt or receive_detect
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or receive_detect_pulse or cfg_uni_mac_mode_change)
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dinesha |
begin
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mii_tx_nxt_st = mii_tx_cur_st;
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tx_en_in = 1'b0;
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tx_pre_in = 1'b0;
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tx_sfd_in = 1'b0;
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tx_err_in = 1'b0;
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tx_ext_in = 1'b0;
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inc_preamble_cntr = 1'b0;
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rst_preamble_cntr = 1'b0;
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tx_xfr_ack_in = 1'b0;
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casex(mii_tx_cur_st) // synopsys parallel_case full_case
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mii_tx_idle_st:
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// wait from start from transmit state machine
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begin
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if(tx2mi_strt_preamble)
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begin
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inc_preamble_cntr = 1'b1;
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tx_en_in = 1'b1;
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tx_pre_in = 1'b1;
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mii_tx_nxt_st = mii_tx_pre_st;
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end
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else
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mii_tx_nxt_st = mii_tx_idle_st;
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end
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332 |
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mii_tx_pre_st:
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334 |
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// This state generates the preamble to be transmitted and
|
335 |
|
|
// generates SFD before transitioning the data state
|
336 |
|
|
begin
|
337 |
|
|
if((tx_preamble_cnt_val == NO_GMII_PREAMBLE) && cf_mac_mode)
|
338 |
|
|
begin
|
339 |
|
|
tx_en_in = 1'b1;
|
340 |
|
|
tx_sfd_in = 1'b1;
|
341 |
|
|
tx_xfr_ack_in = 1'b1;
|
342 |
|
|
rst_preamble_cntr = 1'b1;
|
343 |
|
|
mii_tx_nxt_st = mii_tx_byte_st;
|
344 |
|
|
end
|
345 |
|
|
else if((tx_preamble_cnt_val == NO_MII_PREAMBLE) && !cf_mac_mode &&
|
346 |
|
|
!cf2mi_rmii_en)
|
347 |
|
|
begin
|
348 |
|
|
tx_en_in = 1'b1;
|
349 |
|
|
tx_sfd_in = 1'b1;
|
350 |
|
|
tx_xfr_ack_in = 1'b1;
|
351 |
|
|
rst_preamble_cntr = 1'b1;
|
352 |
|
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
353 |
|
|
end
|
354 |
|
|
else if((tx_preamble_cnt_val == NO_RMII_PREAMBLE) && !cf_mac_mode &&
|
355 |
|
|
cf2mi_rmii_en)
|
356 |
|
|
begin
|
357 |
|
|
tx_en_in = 1'b1;
|
358 |
|
|
tx_sfd_in = 1'b1;
|
359 |
|
|
tx_xfr_ack_in = 1'b1;
|
360 |
|
|
rst_preamble_cntr = 1'b1;
|
361 |
|
|
mii_tx_nxt_st = mii_tx_dibit_st;
|
362 |
|
|
end
|
363 |
|
|
else
|
364 |
|
|
begin
|
365 |
|
|
inc_preamble_cntr = 1'b1;
|
366 |
|
|
tx_en_in = 1'b1;
|
367 |
|
|
tx_pre_in = 1'b1;
|
368 |
|
|
mii_tx_nxt_st = mii_tx_pre_st;
|
369 |
|
|
end
|
370 |
|
|
end
|
371 |
|
|
|
372 |
|
|
mii_tx_byte_st:
|
373 |
|
|
// This state picks up a byte from the transmit block
|
374 |
|
|
// before transmitting on the line
|
375 |
|
|
begin
|
376 |
|
|
if(tx2mi_end_transmit && byte_boundary_tx )
|
377 |
|
|
begin
|
378 |
|
|
tx_en_in = 1'b1;
|
379 |
|
|
tx_xfr_ack_in = 1'b0;
|
380 |
|
|
mii_tx_nxt_st = mii_tx_end_st;
|
381 |
|
|
end
|
382 |
|
|
else if (!cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
|
383 |
|
|
begin
|
384 |
|
|
tx_en_in = 1'b1;
|
385 |
|
|
tx_xfr_ack_in = 1'b1;
|
386 |
|
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
387 |
|
|
end
|
388 |
|
|
else
|
389 |
|
|
begin
|
390 |
|
|
tx_en_in = 1'b1;
|
391 |
|
|
tx_xfr_ack_in = 1'b1;
|
392 |
|
|
mii_tx_nxt_st = mii_tx_byte_st;
|
393 |
|
|
end
|
394 |
|
|
end
|
395 |
|
|
|
396 |
|
|
/*mii_tx_byte_st:
|
397 |
|
|
// This state picks up a byte from the transmit block
|
398 |
|
|
// before transmitting on the line
|
399 |
|
|
begin
|
400 |
|
|
if(tx2mi_end_transmit && byte_boundary_tx )
|
401 |
|
|
begin
|
402 |
|
|
tx_en_in = 1'b1;
|
403 |
|
|
tx_xfr_ack_in = 1'b0;
|
404 |
|
|
mii_tx_nxt_st = mii_tx_end_st;
|
405 |
|
|
end
|
406 |
|
|
else
|
407 |
|
|
begin
|
408 |
|
|
tx_en_in = 1'b1;
|
409 |
|
|
tx_xfr_ack_in = 1'b1;
|
410 |
|
|
mii_tx_nxt_st = mii_tx_byte_st;
|
411 |
|
|
end
|
412 |
|
|
end*/
|
413 |
|
|
|
414 |
|
|
mii_tx_end_st:
|
415 |
|
|
// This state checks for the end of transfer
|
416 |
|
|
// and extend for carrier extension
|
417 |
|
|
begin
|
418 |
|
|
if(tx2mi_strt_preamble)
|
419 |
|
|
begin
|
420 |
|
|
tx_en_in = 1'b1;
|
421 |
|
|
tx_pre_in = 1'b1;
|
422 |
|
|
mii_tx_nxt_st = mii_tx_pre_st;
|
423 |
|
|
end
|
424 |
|
|
else
|
425 |
|
|
begin
|
426 |
|
|
tx_en_in = 1'b0;
|
427 |
|
|
mii_tx_nxt_st = mii_tx_idle_st;
|
428 |
|
|
end
|
429 |
|
|
end
|
430 |
|
|
|
431 |
|
|
/*mii_tx_nibble_st:
|
432 |
|
|
// This state picks up a byte from the transmit block
|
433 |
|
|
// before transmitting on the line
|
434 |
|
|
begin
|
435 |
|
|
if(tx2mi_end_transmit && !byte_boundary_tx )
|
436 |
|
|
begin
|
437 |
|
|
tx_en_in = 1'b1;
|
438 |
|
|
tx_xfr_ack_in = 1'b1;
|
439 |
|
|
mii_tx_nxt_st = mii_tx_nibble_end_st;
|
440 |
|
|
end
|
441 |
|
|
else
|
442 |
|
|
begin
|
443 |
|
|
tx_en_in = 1'b1;
|
444 |
|
|
tx_xfr_ack_in = 1'b1;
|
445 |
|
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
446 |
|
|
end
|
447 |
|
|
end*/
|
448 |
|
|
|
449 |
|
|
mii_tx_nibble_st: // Mandar
|
450 |
|
|
// This state picks up a byte from the transmit block
|
451 |
|
|
// before transmitting on the line
|
452 |
|
|
begin
|
453 |
|
|
if(tx2mi_end_transmit && !byte_boundary_tx )
|
454 |
|
|
begin
|
455 |
|
|
tx_en_in = 1'b1;
|
456 |
|
|
tx_xfr_ack_in = 1'b1;
|
457 |
|
|
mii_tx_nxt_st = mii_tx_nibble_end_st;
|
458 |
|
|
end
|
459 |
|
|
else if (cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
|
460 |
|
|
begin
|
461 |
|
|
tx_en_in = 1'b1;
|
462 |
|
|
tx_xfr_ack_in = 1'b1;
|
463 |
|
|
mii_tx_nxt_st = mii_tx_byte_st;
|
464 |
|
|
end
|
465 |
|
|
else
|
466 |
|
|
begin
|
467 |
|
|
tx_en_in = 1'b1;
|
468 |
|
|
tx_xfr_ack_in = 1'b1;
|
469 |
|
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
470 |
|
|
end
|
471 |
|
|
end
|
472 |
|
|
|
473 |
|
|
mii_tx_nibble_end_st:
|
474 |
|
|
// This state checks for the end of transfer
|
475 |
|
|
// and extend for carrier extension
|
476 |
|
|
begin
|
477 |
|
|
if(tx2mi_strt_preamble)
|
478 |
|
|
begin
|
479 |
|
|
tx_en_in = 1'b1;
|
480 |
|
|
tx_pre_in = 1'b1;
|
481 |
|
|
mii_tx_nxt_st = mii_tx_pre_st;
|
482 |
|
|
end
|
483 |
|
|
else
|
484 |
|
|
begin
|
485 |
|
|
tx_en_in = 1'b0;
|
486 |
|
|
mii_tx_nxt_st = mii_tx_idle_st;
|
487 |
|
|
end
|
488 |
|
|
end
|
489 |
|
|
|
490 |
|
|
mii_tx_dibit_st:
|
491 |
|
|
// This state picks up a byte from the transmit block
|
492 |
|
|
// before transmitting on the line
|
493 |
|
|
begin
|
494 |
|
|
if(tx2mi_end_transmit && (tx_xfr_cnt[0]) && (tx_xfr_cnt[1]) )
|
495 |
|
|
begin
|
496 |
|
|
tx_en_in = 1'b1;
|
497 |
|
|
tx_xfr_ack_in = 1'b1;
|
498 |
|
|
mii_tx_nxt_st = mii_tx_dibit_end_st;
|
499 |
|
|
end
|
500 |
|
|
else
|
501 |
|
|
begin
|
502 |
|
|
tx_en_in = 1'b1;
|
503 |
|
|
tx_xfr_ack_in = 1'b1;
|
504 |
|
|
mii_tx_nxt_st = mii_tx_dibit_st;
|
505 |
|
|
end
|
506 |
|
|
end
|
507 |
|
|
|
508 |
|
|
mii_tx_dibit_end_st:
|
509 |
|
|
// This state checks for the end of transfer
|
510 |
|
|
// and extend for carrier extension
|
511 |
|
|
begin
|
512 |
|
|
if(tx2mi_strt_preamble)
|
513 |
|
|
begin
|
514 |
|
|
tx_en_in = 1'b1;
|
515 |
|
|
tx_pre_in = 1'b1;
|
516 |
|
|
mii_tx_nxt_st = mii_tx_pre_st;
|
517 |
|
|
end
|
518 |
|
|
else
|
519 |
|
|
begin
|
520 |
|
|
tx_en_in = 1'b1;
|
521 |
|
|
mii_tx_nxt_st = mii_tx_idle_st;
|
522 |
|
|
end
|
523 |
|
|
end
|
524 |
|
|
endcase
|
525 |
|
|
end // end always
|
526 |
|
|
|
527 |
|
|
// All the data, enable and ack signals leaving this blocks are
|
528 |
|
|
// registered tx_data and tx_en are outputs going to PHY tx_nibble_ack
|
529 |
|
|
// is indicating to the TX block of acceptance of data nibble
|
530 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
531 |
|
|
begin
|
532 |
|
|
if(!tx_reset_n)
|
533 |
|
|
begin
|
534 |
|
|
lb_tx_en <= 1'b0;
|
535 |
|
|
lb_tx_er <= 1'b0;
|
536 |
|
|
phy_tx_en <= 1'b0;
|
537 |
|
|
phy_tx_er <= 1'b0;
|
538 |
|
|
mi2tx_byte_ack <= 1'b0;
|
539 |
|
|
mi2tx_slot_vld <= 1'b0;
|
540 |
|
|
end
|
541 |
|
|
else
|
542 |
|
|
begin
|
543 |
|
|
lb_tx_en <= tx_en_in;
|
544 |
|
|
lb_tx_er <= tx_err_in;
|
545 |
|
|
phy_tx_en <= (cf_silent_mode) ? 1'b0 : tx_en_in;
|
546 |
|
|
phy_tx_er <= (cf_silent_mode) ? 1'b0 : tx_err_in;
|
547 |
|
|
mi2tx_byte_ack <= (cf_mac_mode || (cf2mi_rmii_en && tx_xfr_cnt[1] && !tx_xfr_cnt[0]) ||
|
548 |
|
|
(!cf2mi_rmii_en && nibble_check_tx)) ? tx_xfr_ack_in : 1'b0;
|
549 |
|
|
mi2tx_slot_vld <= (cf_mac_mode || (cf2mi_rmii_en && tx_slot_xfr_cnt[1] && !tx_slot_xfr_cnt[0]) ||
|
550 |
|
|
(!cf2mi_rmii_en && tx_slot_xfr_cnt[0] )) ? (tx_xfr_ack_in || inc_preamble_cntr) : 1'b0;
|
551 |
|
|
end
|
552 |
|
|
end
|
553 |
|
|
|
554 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
555 |
|
|
begin
|
556 |
|
|
if(!tx_reset_n)
|
557 |
|
|
begin
|
558 |
|
|
phy_txd[7:0] <= 8'b00000000;
|
559 |
|
|
end
|
560 |
|
|
else
|
561 |
|
|
begin
|
562 |
|
|
if (cf_mac_mode)
|
563 |
|
|
phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
|
564 |
37 |
dinesha |
8'b11010101 : ((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte));
|
565 |
12 |
dinesha |
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
566 |
|
|
phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
|
567 |
37 |
dinesha |
4'b1101 : tx_nibble_in) ;
|
568 |
12 |
dinesha |
else if (!cf_mac_mode && cf2mi_rmii_en)
|
569 |
|
|
phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
|
570 |
37 |
dinesha |
2'b11 : tx_dibit_in) ;
|
571 |
12 |
dinesha |
end
|
572 |
|
|
end
|
573 |
|
|
assign receive_detect_pulse = receive_detect && !d_receive_detect;
|
574 |
|
|
|
575 |
|
|
|
576 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
577 |
|
|
begin
|
578 |
|
|
if(!tx_reset_n)
|
579 |
|
|
d_receive_detect <= 0;
|
580 |
|
|
else
|
581 |
|
|
d_receive_detect <= receive_detect;
|
582 |
|
|
end
|
583 |
|
|
// counter for the number transfers
|
584 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
585 |
|
|
begin
|
586 |
|
|
if(!tx_reset_n)
|
587 |
|
|
tx_xfr_cnt <= 2'd0;
|
588 |
|
|
else if(tx2mi_strt_preamble)
|
589 |
|
|
tx_xfr_cnt <= 2'd0;
|
590 |
|
|
else if(tx_xfr_ack_in)
|
591 |
|
|
tx_xfr_cnt <= tx_xfr_cnt + 1;
|
592 |
|
|
end
|
593 |
|
|
|
594 |
|
|
// phy_tx_en_dly
|
595 |
|
|
reg phy_tx_en_dly;
|
596 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
597 |
|
|
begin
|
598 |
|
|
if(!tx_reset_n)
|
599 |
|
|
phy_tx_en_dly <= 1'd0;
|
600 |
|
|
else
|
601 |
|
|
phy_tx_en_dly <= phy_tx_en;
|
602 |
|
|
end
|
603 |
|
|
|
604 |
|
|
wire phy_tx_en_fall;
|
605 |
|
|
assign phy_tx_en_fall = phy_tx_en_dly && !phy_tx_en;
|
606 |
|
|
|
607 |
|
|
// counter for the number transfers ...
|
608 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
609 |
|
|
begin
|
610 |
|
|
if(!tx_reset_n)
|
611 |
|
|
tx_slot_xfr_cnt <= 2'd0;
|
612 |
|
|
else if(phy_tx_en_fall)
|
613 |
|
|
tx_slot_xfr_cnt <= 2'd0;
|
614 |
|
|
else if(inc_preamble_cntr || tx_xfr_ack_in)
|
615 |
|
|
tx_slot_xfr_cnt <= tx_slot_xfr_cnt + 1;
|
616 |
|
|
end
|
617 |
|
|
|
618 |
|
|
assign nibble_check_tx = tx_xfr_cnt[0];
|
619 |
|
|
assign dibit_check_tx= tx_xfr_cnt[0] && tx_xfr_cnt[1];
|
620 |
|
|
assign byte_boundary_tx = (cf_mac_mode) ? 1'b1:
|
621 |
|
|
((!cf_mac_mode && !cf2mi_rmii_en) ? nibble_check_tx : dibit_check_tx);
|
622 |
|
|
|
623 |
|
|
assign tx_nibble_in = (tx_xfr_cnt[0]) ? tx2mi_tx_byte[3:0] : tx2mi_tx_byte[7:4];
|
624 |
|
|
|
625 |
|
|
/* always @(tx_xfr_cnt or tx2mi_tx_byte or phy_tx_clk)
|
626 |
|
|
begin
|
627 |
|
|
if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
628 |
|
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
629 |
|
|
else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
630 |
|
|
tx_dibit_in <= tx2mi_tx_byte[3:2];
|
631 |
|
|
else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
632 |
|
|
tx_dibit_in <= tx2mi_tx_byte[5:4];
|
633 |
|
|
else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
634 |
|
|
tx_dibit_in <= tx2mi_tx_byte[7:6];
|
635 |
|
|
else
|
636 |
|
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
637 |
|
|
end
|
638 |
|
|
*/
|
639 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
640 |
|
|
begin
|
641 |
|
|
if(!tx_reset_n)
|
642 |
|
|
tx_dibit_in <= 2'b0;
|
643 |
|
|
else if(tx2mi_strt_preamble)
|
644 |
|
|
tx_dibit_in <= 2'b0;
|
645 |
|
|
else
|
646 |
|
|
begin
|
647 |
|
|
if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
648 |
|
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
649 |
|
|
else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
650 |
|
|
tx_dibit_in <= tx2mi_tx_byte[3:2];
|
651 |
|
|
else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
652 |
|
|
tx_dibit_in <= tx2mi_tx_byte[5:4];
|
653 |
|
|
else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
654 |
|
|
tx_dibit_in <= tx2mi_tx_byte[7:6];
|
655 |
|
|
end
|
656 |
|
|
end
|
657 |
|
|
|
658 |
|
|
// counter for the number of preamble to be sent
|
659 |
|
|
// before transmitting the sfd
|
660 |
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
661 |
|
|
begin
|
662 |
|
|
if(!tx_reset_n)
|
663 |
|
|
tx_preamble_cnt_val <= 5'd0;
|
664 |
|
|
else if(rst_preamble_cntr)
|
665 |
|
|
tx_preamble_cnt_val <= 5'd0;
|
666 |
|
|
else if(inc_preamble_cntr)
|
667 |
|
|
tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
|
668 |
|
|
end
|
669 |
|
|
|
670 |
|
|
|
671 |
|
|
|
672 |
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
673 |
|
|
begin
|
674 |
|
|
if(!rx_reset_n)
|
675 |
|
|
rx_dfl_dn_reg <= 1'b0;
|
676 |
|
|
else if (df2rx_dfl_dn)
|
677 |
|
|
rx_dfl_dn_reg <= 1'b1;
|
678 |
|
|
else
|
679 |
|
|
begin
|
680 |
|
|
if (!phy_rx_dv && !phy_rx_er)
|
681 |
|
|
rx_dfl_dn_reg <= 1'b0;
|
682 |
|
|
end
|
683 |
|
|
end
|
684 |
|
|
|
685 |
|
|
assign mi2rx_rx_byte = mi2rx_rx_byte_in;
|
686 |
|
|
//assign rxd = (!cf_mac_mode && cf2mi_rmii_en)? mi2rx_rx_byte : mi2rx_rx_byte_in;
|
687 |
|
|
|
688 |
|
|
assign pre_condition_gmii = (!rxd[7] && rxd[6] && !rxd[5] && rxd[4]
|
689 |
|
|
&& !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
690 |
|
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
691 |
|
|
|
692 |
|
|
assign pre_condition_mii = (!rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
693 |
|
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
694 |
|
|
|
695 |
|
|
assign pre_condition_rmii = (!rxd[1] && rxd[0] && rx_dv
|
696 |
|
|
&& !rxd_del[1] && rxd_del[0] && rx_dv_del
|
697 |
|
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
698 |
|
|
|
699 |
|
|
assign sfd_condition_gmii = (rxd[7] && rxd[6] && !rxd[5] && rxd[4]
|
700 |
|
|
&& !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
701 |
|
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
702 |
|
|
|
703 |
|
|
assign sfd_condition_mii = (rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
704 |
|
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
705 |
|
|
|
706 |
|
|
assign sfd_condition_rmii = (rxd[1] && rxd[0] && rx_dv
|
707 |
|
|
&& !rxd_del[1] && rxd_del[0] && rx_dv_del
|
708 |
|
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
709 |
|
|
|
710 |
|
|
|
711 |
|
|
|
712 |
|
|
assign pre_condition = (cf_mac_mode) ? pre_condition_gmii :
|
713 |
|
|
((cf2mi_rmii_en) ? pre_condition_rmii : pre_condition_mii);
|
714 |
|
|
|
715 |
|
|
assign sfd_condition = (cf_mac_mode) ? sfd_condition_gmii :
|
716 |
|
|
((cf2mi_rmii_en) ? sfd_condition_rmii : sfd_condition_mii);
|
717 |
|
|
|
718 |
|
|
// Following state machine is to detect strt preamble and
|
719 |
|
|
// receive preamble and sfd and then the data.
|
720 |
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
721 |
|
|
begin
|
722 |
|
|
if(!rx_reset_n)
|
723 |
|
|
begin
|
724 |
|
|
mii_rx_cur_st <= mii_rx_idle_st;
|
725 |
|
|
end
|
726 |
|
|
else
|
727 |
|
|
begin
|
728 |
|
|
mii_rx_cur_st <= mii_rx_nxt_st;
|
729 |
|
|
end
|
730 |
|
|
end
|
731 |
|
|
|
732 |
|
|
always @(mii_rx_cur_st or rx_dv or rx_er or pre_condition or sfd_condition
|
733 |
|
|
or byte_boundary_rx or rxd or rx_xfr_cnt or cf2mi_rmii_en or cf_mac_mode)
|
734 |
|
|
begin
|
735 |
|
|
mii_rx_nxt_st = mii_rx_cur_st;
|
736 |
|
|
strt_rcv_in = 1'b0;
|
737 |
|
|
end_rcv_in = 1'b0;
|
738 |
|
|
rcv_valid_in = 1'b0;
|
739 |
|
|
rcv_err_in = 1'b0;
|
740 |
|
|
mi2rx_extend_in = 1'b0;
|
741 |
|
|
mi2rx_extend_err_in = 1'b0;
|
742 |
|
|
mi2rx_end_frame_in = 1'b0;
|
743 |
|
|
|
744 |
|
|
casex(mii_rx_cur_st) // synopsys parallel_case full_case
|
745 |
|
|
|
746 |
|
|
mii_rx_idle_st:
|
747 |
|
|
// This state is waiting for pre-amble to
|
748 |
|
|
// appear on the line in Receive mode
|
749 |
|
|
begin
|
750 |
|
|
if(pre_condition)
|
751 |
|
|
mii_rx_nxt_st = mii_rx_pre_st;
|
752 |
|
|
else
|
753 |
|
|
mii_rx_nxt_st = mii_rx_idle_st;
|
754 |
|
|
end
|
755 |
|
|
|
756 |
|
|
mii_rx_pre_st:
|
757 |
|
|
// This state checks the pre-amble and Waits for SFD on the line
|
758 |
|
|
begin
|
759 |
|
|
if(sfd_condition)
|
760 |
|
|
begin
|
761 |
|
|
strt_rcv_in = 1'b1;
|
762 |
|
|
if(cf_mac_mode)
|
763 |
|
|
mii_rx_nxt_st = mii_rx_byte_st;
|
764 |
|
|
else if(!cf_mac_mode && !cf2mi_rmii_en)
|
765 |
|
|
mii_rx_nxt_st = mii_rx_nibble_st;
|
766 |
|
|
else if(!cf_mac_mode && cf2mi_rmii_en)
|
767 |
|
|
mii_rx_nxt_st = mii_rx_dibit_st;
|
768 |
|
|
end
|
769 |
|
|
else if(pre_condition)
|
770 |
|
|
begin
|
771 |
|
|
mii_rx_nxt_st = mii_rx_pre_st;
|
772 |
|
|
end
|
773 |
|
|
else if(!rx_dv && rx_er && cf_mac_mode)
|
774 |
|
|
begin
|
775 |
|
|
mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
|
776 |
|
|
mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
|
777 |
|
|
mii_rx_nxt_st = mii_rx_pre_st;
|
778 |
|
|
end
|
779 |
|
|
else
|
780 |
|
|
begin
|
781 |
|
|
mi2rx_end_frame_in = 1'b1;
|
782 |
|
|
mii_rx_nxt_st = mii_rx_idle_st;
|
783 |
|
|
end
|
784 |
|
|
end
|
785 |
|
|
|
786 |
|
|
mii_rx_byte_st:
|
787 |
|
|
// This state looks for data validity and latches di-bit2 and
|
788 |
|
|
// sends it to the receiver
|
789 |
|
|
begin
|
790 |
|
|
if(rx_dv)
|
791 |
|
|
begin
|
792 |
|
|
rcv_valid_in = 1'b1;
|
793 |
|
|
mii_rx_nxt_st = mii_rx_byte_st;
|
794 |
|
|
end
|
795 |
|
|
else if (!rx_dv && rx_er && cf_mac_mode)
|
796 |
|
|
begin
|
797 |
|
|
mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
|
798 |
|
|
mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
|
799 |
|
|
end_rcv_in = 1'b1;
|
800 |
|
|
mii_rx_nxt_st = mii_rx_pre_st;
|
801 |
|
|
end
|
802 |
|
|
else
|
803 |
|
|
begin
|
804 |
|
|
end_rcv_in = 1'b1;
|
805 |
|
|
mii_rx_nxt_st = mii_rx_end_st;
|
806 |
|
|
end
|
807 |
|
|
end
|
808 |
|
|
|
809 |
|
|
mii_rx_end_st:
|
810 |
|
|
// This state looks for data validity and latches di-bit2 and
|
811 |
|
|
// sends it to the receiver
|
812 |
|
|
mii_rx_nxt_st = mii_rx_idle_st;
|
813 |
|
|
|
814 |
|
|
mii_rx_nibble_st:
|
815 |
|
|
begin
|
816 |
|
|
if(rx_dv)
|
817 |
|
|
begin
|
818 |
|
|
rcv_valid_in = 1'b1;
|
819 |
|
|
mii_rx_nxt_st = mii_rx_nibble_st;
|
820 |
|
|
end
|
821 |
|
|
else
|
822 |
|
|
begin
|
823 |
|
|
end_rcv_in = 1'b1;
|
824 |
|
|
mii_rx_nxt_st = mii_rx_end_st;
|
825 |
|
|
if(rx_xfr_cnt[0])
|
826 |
|
|
rcv_err_in = 1'b1;
|
827 |
|
|
end
|
828 |
|
|
end
|
829 |
|
|
|
830 |
|
|
mii_rx_dibit_st:
|
831 |
|
|
begin
|
832 |
|
|
if(rx_dv)
|
833 |
|
|
begin
|
834 |
|
|
rcv_valid_in = 1'b1;
|
835 |
|
|
mii_rx_nxt_st = mii_rx_dibit_st;
|
836 |
|
|
end
|
837 |
|
|
else
|
838 |
|
|
begin
|
839 |
|
|
end_rcv_in = 1'b1;
|
840 |
|
|
mii_rx_nxt_st = mii_rx_end_st;
|
841 |
|
|
if(!(!rx_xfr_cnt[0] && !rx_xfr_cnt[1]))
|
842 |
|
|
rcv_err_in = 1'b1;
|
843 |
|
|
end
|
844 |
|
|
end
|
845 |
|
|
|
846 |
|
|
endcase
|
847 |
|
|
end // always @ (mii_rx_cur_st...
|
848 |
|
|
|
849 |
|
|
// counter for the number receives
|
850 |
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
851 |
|
|
begin
|
852 |
|
|
if(!rx_reset_n)
|
853 |
|
|
rx_xfr_cnt <= 2'd0;
|
854 |
|
|
else if(mi2rx_end_rcv)
|
855 |
|
|
rx_xfr_cnt <= 2'd0;
|
856 |
|
|
else if(rcv_valid_in)
|
857 |
|
|
rx_xfr_cnt <= rx_xfr_cnt + 1;
|
858 |
|
|
end
|
859 |
|
|
|
860 |
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
861 |
|
|
begin
|
862 |
|
|
if(!rx_reset_n)
|
863 |
|
|
begin
|
864 |
|
|
mi2rx_rx_byte_in <= 8'b0;
|
865 |
|
|
rxd <= 8'b0;
|
866 |
|
|
rxd_del <= 2'b0;
|
867 |
|
|
end
|
868 |
|
|
else
|
869 |
|
|
begin
|
870 |
|
|
rxd <= rxd_in;
|
871 |
|
|
// rxd_del <= rxd_in[1:0];
|
872 |
|
|
rxd_del <= rxd[1:0];
|
873 |
|
|
|
874 |
|
|
if (cf_mac_mode)
|
875 |
|
|
mi2rx_rx_byte_in <= rxd;
|
876 |
|
|
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
877 |
|
|
begin
|
878 |
|
|
if(!rx_xfr_cnt[0])
|
879 |
|
|
mi2rx_rx_byte_in[3:0] <= rxd[3:0];
|
880 |
|
|
else
|
881 |
|
|
mi2rx_rx_byte_in[7:4] <= rxd[3:0];
|
882 |
|
|
end
|
883 |
|
|
else if(!cf_mac_mode && cf2mi_rmii_en)
|
884 |
|
|
begin
|
885 |
|
|
if(!rx_xfr_cnt[1] && !rx_xfr_cnt[0])
|
886 |
|
|
mi2rx_rx_byte_in[1:0] <= rxd[1:0];
|
887 |
|
|
else if(!rx_xfr_cnt[1] && rx_xfr_cnt[0])
|
888 |
|
|
mi2rx_rx_byte_in[3:2] <= rxd[1:0];
|
889 |
|
|
else if(rx_xfr_cnt[1] && !rx_xfr_cnt[0])
|
890 |
|
|
mi2rx_rx_byte_in[5:4] <= rxd[1:0];
|
891 |
|
|
else if(rx_xfr_cnt[1] && rx_xfr_cnt[0])
|
892 |
|
|
mi2rx_rx_byte_in[7:6] <= rxd[1:0];
|
893 |
|
|
end
|
894 |
|
|
end
|
895 |
|
|
end
|
896 |
|
|
|
897 |
|
|
reg rx_sts_rx_er_reg;
|
898 |
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n) begin
|
899 |
|
|
if(!rx_reset_n) begin
|
900 |
|
|
rx_sts_rx_er_reg <= 1'b0;
|
901 |
|
|
end
|
902 |
|
|
else if (mi2rx_strt_rcv) begin
|
903 |
|
|
rx_sts_rx_er_reg <= 1'b0;
|
904 |
|
|
end
|
905 |
|
|
else if(phy_rx_dv && phy_rx_er) begin
|
906 |
|
|
rx_sts_rx_er_reg <= 1'b1;
|
907 |
|
|
end
|
908 |
|
|
end
|
909 |
|
|
|
910 |
|
|
always @(posedge phy_rx_clk
|
911 |
|
|
or negedge rx_reset_n)
|
912 |
|
|
begin
|
913 |
|
|
if(!rx_reset_n)
|
914 |
|
|
begin
|
915 |
|
|
mi2rx_rcv_vld <= 1'b0;
|
916 |
|
|
end
|
917 |
|
|
else if(cf_mac_mode)
|
918 |
|
|
mi2rx_rcv_vld <= rcv_valid_in;
|
919 |
|
|
else if(!cf_mac_mode && cf2mi_rmii_en && rx_xfr_cnt[0] && rx_xfr_cnt[1])
|
920 |
|
|
mi2rx_rcv_vld <= rcv_valid_in;
|
921 |
|
|
else if(!cf_mac_mode && !cf2mi_rmii_en && rx_xfr_cnt[0])
|
922 |
|
|
mi2rx_rcv_vld <= rcv_valid_in;
|
923 |
|
|
else
|
924 |
|
|
mi2rx_rcv_vld <= 1'b0;
|
925 |
|
|
end
|
926 |
|
|
// All the data, enable and ack signals out of RX block are
|
927 |
|
|
// registered
|
928 |
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
929 |
|
|
begin
|
930 |
|
|
if(!rx_reset_n)
|
931 |
|
|
begin
|
932 |
|
|
mi2rx_strt_rcv <= 1'b0;
|
933 |
|
|
mi2rx_end_rcv <= 1'b0;
|
934 |
|
|
//mi2rx_rcv_vld <= 1'b0;
|
935 |
|
|
mi2rx_frame_err <= 1'b0;
|
936 |
|
|
mi2rx_extend <= 1'b0;
|
937 |
|
|
mi2rx_extend_err <= 1'b0;
|
938 |
|
|
mi2rx_end_frame <= 1'b0;
|
939 |
|
|
rx_dv <= 1'b0;
|
940 |
|
|
rx_er <= 1'b0;
|
941 |
|
|
rx_dv_del <= 1'b0;
|
942 |
|
|
end
|
943 |
|
|
else
|
944 |
|
|
begin
|
945 |
|
|
mi2rx_strt_rcv <= strt_rcv_in;
|
946 |
|
|
mi2rx_end_rcv <= end_rcv_in;
|
947 |
|
|
//mi2rx_rcv_vld <= rcv_valid_in;
|
948 |
|
|
mi2rx_frame_err <= rcv_err_in;
|
949 |
|
|
mi2rx_extend <= mi2rx_extend_in;
|
950 |
|
|
mi2rx_extend_err <= mi2rx_extend_err_in;
|
951 |
|
|
mi2rx_end_frame <= mi2rx_end_frame_in;
|
952 |
|
|
rx_dv <= rx_dv_in;
|
953 |
|
|
rx_er <= rx_er_in;
|
954 |
|
|
rx_dv_del <= rx_dv;
|
955 |
|
|
end
|
956 |
|
|
end
|
957 |
|
|
|
958 |
|
|
|
959 |
|
|
|
960 |
|
|
half_dup_dble_reg U_dble_reg1 (
|
961 |
|
|
//outputs
|
962 |
|
|
.sync_out_pulse(receive_detect),
|
963 |
|
|
//inputs
|
964 |
|
|
.in_pulse(rx_dv_in),
|
965 |
|
|
.dest_clk(phy_tx_clk),
|
966 |
|
|
.reset_n(tx_reset_n)
|
967 |
|
|
);
|
968 |
|
|
|
969 |
|
|
|
970 |
|
|
wire test;
|
971 |
|
|
|
972 |
|
|
half_dup_dble_reg U_dble_reg5 (
|
973 |
|
|
//outputs
|
974 |
|
|
.sync_out_pulse(tx_en),
|
975 |
|
|
//inputs
|
976 |
|
|
.in_pulse(lb_tx_en),
|
977 |
|
|
.dest_clk(phy_rx_clk),
|
978 |
|
|
.reset_n(rx_reset_n)
|
979 |
|
|
);
|
980 |
|
|
|
981 |
|
|
half_dup_dble_reg U_dble_reg6 (
|
982 |
|
|
//outputs
|
983 |
|
|
.sync_out_pulse(txd[0]),
|
984 |
|
|
//inputs
|
985 |
|
|
.in_pulse(phy_txd[0]),
|
986 |
|
|
.dest_clk(phy_rx_clk),
|
987 |
|
|
.reset_n(rx_reset_n)
|
988 |
|
|
);
|
989 |
|
|
|
990 |
|
|
half_dup_dble_reg U_dble_reg7 (
|
991 |
|
|
//outputs
|
992 |
|
|
.sync_out_pulse(txd[1]),
|
993 |
|
|
//inputs
|
994 |
|
|
.in_pulse(phy_txd[1]),
|
995 |
|
|
.dest_clk(phy_rx_clk),
|
996 |
|
|
.reset_n(rx_reset_n)
|
997 |
|
|
);
|
998 |
|
|
|
999 |
|
|
half_dup_dble_reg U_dble_reg8 (
|
1000 |
|
|
//outputs
|
1001 |
|
|
.sync_out_pulse(txd[2]),
|
1002 |
|
|
//inputs
|
1003 |
|
|
.in_pulse(phy_txd[2]),
|
1004 |
|
|
.dest_clk(phy_rx_clk),
|
1005 |
|
|
.reset_n(rx_reset_n)
|
1006 |
|
|
);
|
1007 |
|
|
|
1008 |
|
|
half_dup_dble_reg U_dble_reg9 (
|
1009 |
|
|
//outputs
|
1010 |
|
|
.sync_out_pulse(txd[3]),
|
1011 |
|
|
//inputs
|
1012 |
|
|
.in_pulse(phy_txd[3]),
|
1013 |
|
|
.dest_clk(phy_rx_clk),
|
1014 |
|
|
.reset_n(rx_reset_n)
|
1015 |
|
|
);
|
1016 |
|
|
|
1017 |
|
|
half_dup_dble_reg U_dble_reg10 (
|
1018 |
|
|
//outputs
|
1019 |
|
|
.sync_out_pulse(txd[4]),
|
1020 |
|
|
//inputs
|
1021 |
|
|
.in_pulse(phy_txd[4]),
|
1022 |
|
|
.dest_clk(phy_rx_clk),
|
1023 |
|
|
.reset_n(rx_reset_n)
|
1024 |
|
|
);
|
1025 |
|
|
|
1026 |
|
|
|
1027 |
|
|
half_dup_dble_reg U_dble_reg11 (
|
1028 |
|
|
//outputs
|
1029 |
|
|
.sync_out_pulse(txd[5]),
|
1030 |
|
|
//inputs
|
1031 |
|
|
.in_pulse(phy_txd[5]),
|
1032 |
|
|
.dest_clk(phy_rx_clk),
|
1033 |
|
|
.reset_n(rx_reset_n)
|
1034 |
|
|
);
|
1035 |
|
|
|
1036 |
|
|
|
1037 |
|
|
half_dup_dble_reg U_dble_reg12 (
|
1038 |
|
|
//outputs
|
1039 |
|
|
.sync_out_pulse(txd[6]),
|
1040 |
|
|
//inputs
|
1041 |
|
|
.in_pulse(phy_txd[6]),
|
1042 |
|
|
.dest_clk(phy_rx_clk),
|
1043 |
|
|
.reset_n(rx_reset_n)
|
1044 |
|
|
);
|
1045 |
|
|
|
1046 |
|
|
|
1047 |
|
|
half_dup_dble_reg U_dble_reg13 (
|
1048 |
|
|
//outputs
|
1049 |
|
|
.sync_out_pulse(txd[7]),
|
1050 |
|
|
//inputs
|
1051 |
|
|
.in_pulse(phy_txd[7]),
|
1052 |
|
|
.dest_clk(phy_rx_clk),
|
1053 |
|
|
.reset_n(rx_reset_n)
|
1054 |
|
|
);
|
1055 |
|
|
|
1056 |
|
|
|
1057 |
|
|
half_dup_dble_reg U_dble_reg14 (
|
1058 |
|
|
//outputs
|
1059 |
|
|
.sync_out_pulse(tx_er),
|
1060 |
|
|
//inputs
|
1061 |
|
|
.in_pulse(lb_tx_er),
|
1062 |
|
|
.dest_clk(phy_rx_clk),
|
1063 |
|
|
.reset_n(rx_reset_n)
|
1064 |
|
|
);
|
1065 |
|
|
|
1066 |
|
|
|
1067 |
|
|
half_dup_dble_reg U_dble_reg15 (
|
1068 |
|
|
//outputs
|
1069 |
|
|
.sync_out_pulse(mi2rx_crs),
|
1070 |
|
|
//inputs
|
1071 |
|
|
.in_pulse(crs_in),
|
1072 |
|
|
.dest_clk(phy_rx_clk),
|
1073 |
|
|
.reset_n(rx_reset_n)
|
1074 |
|
|
);
|
1075 |
|
|
|
1076 |
|
|
endmodule
|
1077 |
|
|
|