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1 12 dinesha
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Tubo 8051 cores MAC Interface Module                        ////
4
////                                                              ////
5
////  This file is part of the Turbo 8051 cores project           ////
6
////  http://www.opencores.org/cores/turbo8051/                   ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Turbo 8051 definitions.                                     ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////    nothing                                                   ////
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////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
/***************************************************************
44
 Description:
45
 
46
 rx_fsm.v: This verilog file is the receive state machine for the MAC
47
 block. It receives nibbles from rmii block. It assembles
48
 double words from bytes. Generates writes to Receive FIFO
49
 Removes padding and generates appropriate signals to the
50
 CRC and Address Filtering block. It also generates the necessary
51
 signals to generate status for every frame.
52
 
53
 ***************************************************************/
54
/************** MODULE DECLARATION ****************************/
55
//`timescale 1ns/100ps
56
module g_rx_fsm(
57
                // Status information to Applications
58
                rx_sts_vld,
59
                rx_sts_bytes_rcvd,
60
                rx_sts_large_pkt,
61
                rx_sts_lengthfield_err,
62
                rx_sts_crc_err,
63
                rx_sts_runt_pkt_rcvd,
64
                rx_sts_rx_overrun,
65
                rx_sts_frm_length_err,
66
                rx_sts_len_mismatch,
67
                // Data Signals to Fifo Management Block
68
                clr_rx_error_from_rx_fsm,
69
                rx2ap_rx_fsm_wrt,
70
                rx2ap_rx_fsm_dt,
71
                // Fifo Control Signal to Fifo Management Block
72
                rx2ap_commit_write,
73
                rx2ap_rewind_write,
74
                // To address filtering block
75
                //commit
76
                commit_write_done,
77
 
78
                // Global Signals 
79
                reset_n,
80
                phy_rx_clk,
81
                // Signals from Mii/Rmii block for Receive data 
82
                mi2rx_strt_rcv,
83
                mi2rx_rcv_vld,
84
                mi2rx_rx_byte,
85
                mi2rx_end_rcv,
86
                mi2rx_extend,
87
                mi2rx_frame_err,
88
                mi2rx_end_frame,
89
                // Rx fifo management signal to indicate overrun
90
                rx_fifo_full,
91
                ap2rx_rx_fifo_err,
92
                // Signal from CRC check block
93
                rc2rx_crc_ok,
94
                // Signals from Config Management Block
95
                cf2rx_max_pkt_sz,
96
                cf2rx_rx_ch_en,
97
                cf2rx_strp_pad_en,
98
                cf2rx_snd_crc,
99
                cf2rx_rcv_runt_pkt_en,
100
                cf2rx_gigabit_xfr,
101
      //A200 change Port added for crs based flow control
102 37 dinesha
      phy_crs
103 12 dinesha
 
104
                );
105
 
106
 
107
parameter MIN_FRM_SIZE = 6'h2e        ;
108
  /******* INPUT & OUTPUT DECLARATIONS *************************/
109
  output        rx_sts_vld;                    // Receive status is available for the application
110
  output [15:0] rx_sts_bytes_rcvd;
111
  output        rx_sts_large_pkt;
112
  output        rx_sts_lengthfield_err;
113
  output        rx_sts_crc_err;
114
  output        rx_sts_runt_pkt_rcvd;
115
  output        rx_sts_rx_overrun;
116
  output        rx_sts_frm_length_err;
117
  output        rx_sts_len_mismatch;
118
 
119
  output        rx2ap_rx_fsm_wrt;              // Receive Fifo Write
120
  output [8:0]   rx2ap_rx_fsm_dt;               // This is 32 bit assembled receive data 
121
                                               // with EOP and valid bytes information in it.
122
  output        rx2ap_commit_write;            // This is to RX fifo MGMT to indicate 
123
                                               // that the current packet 
124
                                               // has to be sent to application
125
  output        rx2ap_rewind_write;            // This indicates the previous packet 
126
                                               // in the FIFO has a error
127
                                               // Ignore the packet and restart from the
128
                                               // end of previous packet
129
  output    clr_rx_error_from_rx_fsm;
130
  output    commit_write_done;
131
 
132
  input         reset_n;                               // reset from mac application interface
133
  input         phy_rx_clk;                    // Reference clock used for RX 
134
 
135
  input         mi2rx_strt_rcv;                // Receive data from the PHY
136
  input         mi2rx_rcv_vld;                 // Received nibble is valid
137
  input [7:0]    mi2rx_rx_byte;                 // Rx nibble from the RMII/MII block
138
  input         mi2rx_end_rcv;                 // This is provided by the RMII/MII 
139
                                               // block to indicate
140
                                               // end of receieve
141
  input         mi2rx_frame_err;
142
  input         mi2rx_end_frame;
143
  input         rx_fifo_full;
144
  input         ap2rx_rx_fifo_err;             // Receive error generated by the 
145
                                               // RX FIFO MGMT block
146
 
147
  input         rc2rx_crc_ok;                  // CRC of the receiving packet is OK. 
148
                                               // Generated by CRC block
149
 
150
  input [15:0]  cf2rx_max_pkt_sz;              // max packet size
151
 
152
  input         cf2rx_rx_ch_en;                // Receive Enabled
153
  input         cf2rx_strp_pad_en;             // Do not Append padding after the data
154
  input         cf2rx_snd_crc;                 // Append CRC to the data 
155
                                               // ( This automatically means padding
156
                                               // will be enabled)
157
  input         cf2rx_rcv_runt_pkt_en;         // Receive needs to receive
158
  input         cf2rx_gigabit_xfr;
159
  input         mi2rx_extend;
160
 
161
  //A200 change Port added for crs based flow control
162
  input  phy_crs;
163
 
164
 
165
  /******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
166
  reg           rx2ap_commit_write;
167
  reg           rx2ap_rewind_write;
168
  reg [8:0]      rx2ap_rx_fsm_dt;
169
  reg           rx2ap_rx_fsm_wrt;
170
  wire [31:0]    rx_sts_dt;
171
  reg [31:0]     rx_sts;
172
 
173
  /*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
174
  reg           commit_write;
175
  reg           rewind_write;
176
  wire          look_at_length_field;
177
  reg           send_crc;
178
  reg           rcv_pad_data;
179
  reg           first_dword;
180
  wire [15:0]    inc_rcv_byte_count;
181
  reg [15:0]     rcv_byte_count;
182
  reg           reset_tmp_count;
183
  reg           ld_length_byte_1,ld_length_byte_2;
184
  reg           set_crc_error;
185
  reg           set_byte_allgn_error;
186
  reg           rx_sts_vld,e_rx_sts_vld;
187
  reg           padding_needed;
188
  reg           dec_data_len;
189
  reg           dec_pad_len;
190
  reg           gen_eop;
191
  reg           set_frm_lngth_error;
192
  reg           set_incomplete_frm;
193
  reg           byte_boundary;
194
  reg           error;
195
  reg           error_seen;
196
  reg           commit_write_done;
197
  reg           check_padding;
198
  reg           check_padding_in;
199
  reg [2:0]      padding_len_reg;
200
  reg [15:0]     rcv_length_reg;
201
  reg [15:0]     length_counter;
202
 
203
  reg [18:0]     rx_fsm_cur_st;
204
  reg [18:0]     rx_fsm_nxt_st;
205
  reg           crc_stat_reg;
206
  reg           rx_runt_pkt_reg;
207
  reg           large_pkt_reg;
208
  reg           rx_fifo_overrun_reg;
209
  reg           frm_length_err_reg;
210
  reg [2:0]      crc_count;
211
  reg           inc_shift_counter;
212
  reg           send_data_to_fifo;
213
  wire          send_runt_packet;
214
  reg [2:0]      shift_counter;
215
  reg [2:0]      bytes_to_fifo;
216
  reg [7:0]      buf_latch4,buf_latch3,buf_latch2,buf_latch1,buf_latch0;
217
  wire          ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
218
  reg           lengthfield_error;
219
  reg           lengthfield_err_reg;
220
  reg           addr_stat_chk;
221
  reg           clr_rx_error_from_rx_fsm;
222
 
223
  wire [15:0]    adj_rcv_length_reg;
224
  wire [15:0]    adj_rcv_byte_count;
225
  wire [15:0]    adj_cf2rx_max_pkt_sz;
226
  reg            set_tag1_flag, set_tag2_flag;
227
 
228
  parameter     rx_fsm_idle_st=               19'b0000000000000000000,
229
                rx_fsm_chkdestad_nib1_st =    19'b0000000000000000001,
230
                rx_fsm_lk4srcad_nib1_st =     19'b0000000000000000010,
231
                rx_fsm_lk4len_byte1_st =      19'b0000000000000000100,
232
                rx_fsm_lk4len_byte2_st =      19'b0000000000000001000,
233
                rx_fsm_getdt_nib1_st =        19'b0000000000000010000,
234
                rx_fsm_getpaddt_nib1_st =     19'b0000000000000100000,
235
                rx_fsm_updstat_st =           19'b0000000000001000000,
236
                rx_fsm_chkval_st =            19'b0000000000010000000,
237 37 dinesha
                rx_fsm_extend_st =            19'b0000000100000000000;
238 12 dinesha
 
239
  /***************** WIRE ASSIGNMENTS *************************/
240
  wire [6:0]     dec_pad_length;
241
  wire [15:0]    inc_length_counter;
242
  wire          rx_overrun_error;
243
  wire          commit_condition;
244
 
245
//COMMIT_WRITE CONDITION
246
assign commit_condition = ((inc_rcv_byte_count[14:0] == 15'd65)&& !commit_write_done );
247
 
248
 
249
 
250
  /******** SEQUENTIAL LOGIC **********************************/
251
  half_dup_dble_reg U_dble_reg1 (
252
                        //outputs
253
                        .sync_out_pulse(rx_ch_en),
254
                        //inputs
255
                        .in_pulse(cf2rx_rx_ch_en),
256
                        .dest_clk(phy_rx_clk),
257
                        .reset_n(reset_n)
258
                        );
259
 
260
  // ap2rx_rx_fifo_err signal is generated in rx_clk domain
261
  assign        rx_overrun_error = ap2rx_rx_fifo_err;
262
 
263
  reg           rx_sts_vld_delayed;
264
  always @(posedge phy_rx_clk
265
           or negedge reset_n)
266
    begin
267
      if(!reset_n)
268
        begin
269
          rx_sts <= 32'b0;
270
          rx_sts_vld <= 1'b0;
271
          rx_sts_vld_delayed <= 1'b0;
272
        end
273
      else
274
        begin
275
          rx_sts_vld <= rx_sts_vld_delayed;
276
          rx_sts_vld_delayed <= e_rx_sts_vld;
277
          if (e_rx_sts_vld)
278
            rx_sts <= rx_sts_dt;
279
        end
280
    end
281
 
282
  always @(posedge phy_rx_clk
283
           or negedge reset_n)
284
    begin
285
      if(!reset_n)
286
        begin
287
          rx_fsm_cur_st <= rx_fsm_idle_st;
288
          check_padding <= 1'b0;
289
        end
290
      else
291
        begin
292
          rx_fsm_cur_st <= rx_fsm_nxt_st;
293
          check_padding <= check_padding_in;
294
        end
295
    end
296
  reg first_byte_seen;
297
 
298
 
299
  always @(posedge phy_rx_clk
300
           or negedge reset_n)
301
      if(!reset_n)
302
        first_byte_seen <= 1'b0;
303
      else if(mi2rx_strt_rcv)
304
        first_byte_seen <= 1'b1;
305
      else if(mi2rx_rcv_vld)
306
        first_byte_seen <= 1'b0;
307
 
308
 
309
 
310
// adjust rcv_length reg for packet sizes < 64 bytes
311
assign adj_rcv_length_reg =   (rcv_length_reg < 8'h2E) ? 8'h2E : rcv_length_reg;
312
 
313
// subtr 18 bytes (sa + da + fcs + t/l)
314
assign adj_rcv_byte_count = rcv_byte_count - 8'd18;
315
 
316
// configured max packet size should be 16'd1518.
317
assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
318
 
319
 
320
 
321
  // Following state machine is to receive nibbles from the RMII/MII
322
  // block and packetize them to 32 bits with information of EOP and 
323
  // valid bytes. It also discards packets which are less than minimum
324
  // frame size. It performs Address validity and Data validity.
325
  always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
326 37 dinesha
           or cf2rx_snd_crc or look_at_length_field
327 12 dinesha
           or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
328
           or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
329
           or inc_length_counter or rcv_length_reg or commit_write_done
330
           or crc_count or shift_counter or bytes_to_fifo
331 37 dinesha
            or cf2rx_rcv_runt_pkt_en
332 12 dinesha
           or inc_rcv_byte_count or send_runt_packet
333 37 dinesha
           or rcv_byte_count or first_dword
334 12 dinesha
           or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
335
    begin
336
      rx_fsm_nxt_st = rx_fsm_cur_st;
337
      set_tag1_flag = 1'b0;
338
      set_tag2_flag = 1'b0;
339
      reset_tmp_count = 1'b0;
340
      ld_length_byte_1 = 1'b0;
341
      ld_length_byte_2 = 1'b0;
342
      dec_data_len = 1'b0;
343
      dec_pad_len = 1'b0;
344
      commit_write = 1'b0;
345
      rewind_write = 1'b0;
346
      e_rx_sts_vld = 1'b0;
347
      set_crc_error = 1'b0;
348
      check_padding_in = 1'b0;
349
      set_byte_allgn_error = 1'b0;
350
      set_incomplete_frm = 1'b0;
351
      set_frm_lngth_error = 1'b0;
352
      gen_eop = 1'b0;
353
      error = 1'b0;
354
      byte_boundary= 1'b0;
355
      send_crc = 1'b0;
356
      rcv_pad_data = 1'b0;
357
      inc_shift_counter = 1'b0;
358
      send_data_to_fifo = 1'b0;
359
      lengthfield_error = 1'b0;
360
      addr_stat_chk = 1'b0;
361
      clr_rx_error_from_rx_fsm = 1'b0;
362
 
363
 
364
      casex(rx_fsm_cur_st)       // synopsys parallel_case full_case
365
        rx_fsm_idle_st:
366
          // Waiting for packet from mii block
367
          // Continues accepting data only if
368
          // receive has been enabled
369
          begin
370
            if(ap2rx_rx_fifo_err)
371
                begin
372
                   clr_rx_error_from_rx_fsm = 1'b1;
373
                   rx_fsm_nxt_st = rx_fsm_idle_st;
374
                end
375
            else if (rx_fifo_full)
376
              rx_fsm_nxt_st = rx_fsm_idle_st;
377
            else if(mi2rx_strt_rcv && rx_ch_en )
378
              rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
379
            else
380
              rx_fsm_nxt_st = rx_fsm_idle_st;
381
          end
382
 
383
        rx_fsm_chkdestad_nib1_st:
384
          begin
385
            // collecting the nibbles of destination
386
            // address
387
            if(ap2rx_rx_fifo_err)
388
              begin
389
                rewind_write = 1'b1;
390
                rx_fsm_nxt_st = rx_fsm_idle_st;
391
              end
392
            else if(mi2rx_end_rcv)
393
              begin
394
                if(cf2rx_rcv_runt_pkt_en)
395
                  begin
396
                    rx_fsm_nxt_st = rx_fsm_chkval_st;
397
                    commit_write = 1'b1;
398
                  end
399
                else
400
                  begin
401
                    rx_fsm_nxt_st = rx_fsm_idle_st;
402
                    if (rcv_byte_count[2:0] > 5)
403
                      rewind_write = 1'b1;
404
                  end
405
              end // if (mi2rx_end_rcv)
406
 
407
            else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
408
              begin
409 37 dinesha
                       rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
410 12 dinesha
              end
411
            else
412
              begin
413
                rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
414
              end
415
          end
416
 
417
        rx_fsm_lk4srcad_nib1_st:
418
          // collecting nibbles of source address
419
          // in case of termination of packet
420
          // or carrier sense error then generate eop
421
          // and generate status
422
          begin
423
            if(ap2rx_rx_fifo_err )
424
              begin
425
                rewind_write = 1;
426
                rx_fsm_nxt_st = rx_fsm_idle_st;
427
              end // else: !if(mi2rx_end_rcv)
428
            else if(mi2rx_end_rcv)
429
              begin
430
                if(cf2rx_rcv_runt_pkt_en)
431
                  begin
432
                    rx_fsm_nxt_st = rx_fsm_chkval_st;
433
                    commit_write = 1'b1;
434
                  end
435
                else
436
                  begin
437
                    rx_fsm_nxt_st = rx_fsm_idle_st;
438
                    rewind_write = 1'b1;
439
                  end
440
              end
441
            else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
442
              begin
443
                  rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
444
              end
445
            else
446
              begin
447
                rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
448
              end
449
          end
450
 
451
        rx_fsm_lk4len_byte1_st:
452
          // this state collects the odd nibbles of the length 
453
          // field. 
454
          begin
455
            if(ap2rx_rx_fifo_err)
456
              begin
457
                rewind_write = 1;
458
                rx_fsm_nxt_st = rx_fsm_idle_st;
459
              end // else: !if(mi2rx_end_rcv)
460
            else if(mi2rx_end_rcv)
461
              begin
462
                if(cf2rx_rcv_runt_pkt_en)
463
                  begin
464
                    rx_fsm_nxt_st = rx_fsm_chkval_st;
465
                    commit_write = 1'b1;
466
                  end
467
                else
468
                  begin
469
                    rx_fsm_nxt_st = rx_fsm_idle_st;
470
                    rewind_write = 1'b1;
471
                  end
472
              end
473
            else if(mi2rx_rcv_vld)
474
              begin
475
                ld_length_byte_1 = 1'b1;
476
                rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
477
              end
478
            else
479
              rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
480
          end
481
 
482
        rx_fsm_lk4len_byte2_st:
483
          // This state generates the even nibbles of the length
484
          // field
485
        begin
486
           if(ap2rx_rx_fifo_err )
487
           begin
488
              rewind_write = 1;
489
              rx_fsm_nxt_st = rx_fsm_idle_st;
490
           end // else: !if(mi2rx_end_rcv)
491
           else if(mi2rx_end_rcv)
492
           begin
493
              if(cf2rx_rcv_runt_pkt_en)
494
              begin
495
                 rx_fsm_nxt_st = rx_fsm_chkval_st;
496
                 commit_write = 1'b1;
497
              end
498
              else
499
              begin
500
                 rx_fsm_nxt_st = rx_fsm_idle_st;
501
                 rewind_write = 1'b1;
502
              end
503
           end
504
           else if(mi2rx_rcv_vld )
505
           begin
506
              ld_length_byte_2 = 1'b1;
507
              check_padding_in = 1'b1;
508
              rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
509
           end
510
           else
511
                rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
512
        end // rx_fsm_lk4len_byte2_st
513
 
514
        rx_fsm_getdt_nib1_st: //state number 7
515
          // This state collects the nibbles of the receive data
516
          // This state makes a determination to remove padding
517
          // only if strip padding is enabled and the length field
518
          // detected is less than 64
519
          begin
520
            if  (commit_condition)
521
              commit_write = 1'b1;
522
 
523
            if((ap2rx_rx_fifo_err) && !commit_write_done)
524
              begin
525
                rewind_write = 1;
526
                rx_fsm_nxt_st = rx_fsm_idle_st;
527
              end // else: !if(mi2rx_end_rcv)
528
            else if (ap2rx_rx_fifo_err)
529
              begin
530
                rx_fsm_nxt_st = rx_fsm_updstat_st;
531
              end
532
            else if(mi2rx_end_rcv)
533
              begin
534
                if(cf2rx_rcv_runt_pkt_en && !(commit_write_done | commit_condition))
535
                  begin
536
                    commit_write = 1'b1;
537
                    rx_fsm_nxt_st = rx_fsm_chkval_st;
538
                  end
539
                else if(!(commit_write_done | commit_condition) && !cf2rx_rcv_runt_pkt_en)
540
                  begin
541
                    rewind_write = 1'b1;
542
                    rx_fsm_nxt_st = rx_fsm_idle_st;
543
                  end
544
                else
545
                  rx_fsm_nxt_st = rx_fsm_chkval_st;
546
              end
547
            else if(mi2rx_rcv_vld && (inc_length_counter == rcv_length_reg) &&
548
                    look_at_length_field)
549
              begin
550
                dec_data_len = 1'b1;
551
                rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
552
              end
553
            else if(mi2rx_rcv_vld && look_at_length_field)
554
              begin
555
                dec_data_len = 1'b1;
556
                rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
557
              end
558
            else
559
              rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
560
          end
561
 
562
        rx_fsm_getpaddt_nib1_st:
563
          // This state handles the padded data in case of less than 64
564
          // byte packets This handles the odd nibbles
565
          begin
566
            if(ap2rx_rx_fifo_err)
567
              begin
568
                if(rcv_byte_count[14:0] <= 15'd64) // mfilardo
569
                //if(inc_rcv_byte_count[14:0] <= 15'd64)
570
                  begin
571
                    rewind_write = 1'b1;
572
                    rx_fsm_nxt_st = rx_fsm_idle_st;
573
                  end
574
                else
575
                  rx_fsm_nxt_st = rx_fsm_updstat_st;
576
              end
577
            else if(mi2rx_end_rcv)
578
              begin
579
                //if(inc_rcv_byte_count[14:0] == 15'd64)
580
                if(rcv_byte_count[14:0] == 15'd64) // mfilardo
581
                  lengthfield_error = 0;
582
                else
583
                  lengthfield_error = 1;
584
 
585
                  rx_fsm_nxt_st = rx_fsm_extend_st;
586
              end
587
            else if(mi2rx_rcv_vld)
588
              begin
589
                if(cf2rx_strp_pad_en)
590
                  rcv_pad_data = 1'b1;
591
              end
592
            else
593
              rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
594
          end // case: rx_fsm_getpaddt_nib1_st
595
 
596
 
597
        rx_fsm_extend_st:
598
          //This state handles the first extend conditon in the
599
          //cf2rx_gigabit_xfr
600
          //transfer
601
          begin
602
            if (mi2rx_extend)
603
              begin
604
                  rx_fsm_nxt_st = rx_fsm_extend_st;
605
              end
606
            else
607
              begin
608
                commit_write = 1'b1;
609
                rx_fsm_nxt_st = rx_fsm_chkval_st;
610
              end
611
          end
612
        rx_fsm_chkval_st:
613
          // This packet generates the validity of the packet
614
          // This is reached either on clean or error type
615
          // completion of packet.
616
          begin
617
            if(ap2rx_rx_fifo_err)
618
              begin
619
                rx_fsm_nxt_st = rx_fsm_updstat_st;
620
              end
621
            else if(cf2rx_rcv_runt_pkt_en && first_dword)
622
              begin
623
                rx_fsm_nxt_st = rx_fsm_chkval_st;
624 61 dinesha
                case(rcv_byte_count[2:0])
625 12 dinesha
                  3'd1:
626
                    begin
627
                      if(shift_counter == 3'd4)
628
                        begin
629
                          if(bytes_to_fifo == rcv_byte_count[2:0])
630
                            begin
631
                              gen_eop = 1'b1;
632
                              rx_fsm_nxt_st = rx_fsm_updstat_st;
633
                            end // if (bytes_to_fifo == rcv_nibble_count[3:1])
634
                          else
635
                            send_data_to_fifo = 1'b1;
636
                        end // if (shift_counter == 3'd4)
637
                      else
638
                        inc_shift_counter = 1;
639
                    end // case: 3'd1
640
 
641
                  3'd2:
642
                    begin
643
                      if(shift_counter == 3'd3)
644
                        begin
645
                          if(bytes_to_fifo == rcv_byte_count[2:0])
646
                            begin
647
                              gen_eop = 1'b1;
648
                              rx_fsm_nxt_st = rx_fsm_updstat_st;
649
                            end // if (bytes_to_fifo == rcv_nibble_count[3:1])
650
                          else
651
                            send_data_to_fifo = 1'b1;
652
                        end // if (shift_counter == 3'd3)
653
                      else
654
                        inc_shift_counter = 1;
655
                    end // case: 3'd2
656
 
657
                  3'd3:
658
                    begin
659
                      if(shift_counter == 3'd2)
660
                        begin
661
                          if(bytes_to_fifo == rcv_byte_count[2:0])
662
                            begin
663
                              gen_eop = 1'b1;
664
                              rx_fsm_nxt_st = rx_fsm_updstat_st;
665
                            end
666
                          else
667
                            send_data_to_fifo = 1'b1;
668
                        end // if (shift_counter == 3'd2)
669
                      else
670
                        inc_shift_counter = 1;
671
                    end // case: 3'd3
672
 
673
                  3'd4:
674
                    begin
675
                      if(shift_counter == 3'd1)
676
                        begin
677
                          if(bytes_to_fifo == rcv_byte_count[2:0])
678
                            begin
679
                              gen_eop = 1'b1;
680
                              rx_fsm_nxt_st = rx_fsm_updstat_st;
681
                            end // if (bytes_to_fifo == rcv_nibble_count[3:1])
682
                          else
683
                            send_data_to_fifo = 1'b1;
684
                        end
685
                      else
686
                        inc_shift_counter = 1;
687
                    end // case: 3'd4
688
                  default:
689
                    begin
690
                      rx_fsm_nxt_st = rx_fsm_idle_st;
691
                      gen_eop = 1'b0;
692
                    end
693
                endcase // case(rcv_nibble_count[3
694
              end // if (cf2rx_rcv_runt_pkt_en && first_dword)
695
            else if(((cf2rx_snd_crc || send_runt_packet || look_at_length_field)
696
                     && crc_count == 3'd4))
697
              begin
698
                gen_eop = 1'b1;
699
                rx_fsm_nxt_st = rx_fsm_updstat_st;
700
              end
701
            else if(send_runt_packet || look_at_length_field)
702
              begin
703
                send_crc = 1'b1;
704
                rx_fsm_nxt_st = rx_fsm_chkval_st;
705
              end
706
            else if(!cf2rx_snd_crc)
707
              begin
708
                gen_eop = 1'b1;
709
                rx_fsm_nxt_st = rx_fsm_updstat_st;
710
              end
711
            else
712
              begin
713
                send_crc = 1'b1;
714
                rx_fsm_nxt_st = rx_fsm_chkval_st;
715
              end
716
          end // case: rx_fsm_chkval_st
717
 
718
        rx_fsm_updstat_st:
719
          // This state updates the status to the application
720
          // This allows the application to determine the validity
721
          // of the packet so that it can take the necessary action
722
          begin
723
            e_rx_sts_vld = 1'b1;
724
            rx_fsm_nxt_st = rx_fsm_idle_st;
725
          end
726
 
727
        default:
728
          begin
729
            rx_fsm_nxt_st = rx_fsm_idle_st;
730
          end
731
      endcase // casex(rx_fsm_cur_st)
732
    end // always @ (rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en...
733
 
734
  always @(inc_rcv_byte_count)
735
    begin
736
      if(inc_rcv_byte_count[14:0] < 15'd6)
737
        first_dword = 1'b1;
738
      else
739
        first_dword = 1'b0;
740
    end // always @ (inc_rcv_nibble_count or...
741
 
742
 
743
  always @(posedge phy_rx_clk
744
           or negedge reset_n)
745
    begin
746
      if(!reset_n)
747
        crc_count <= 3'b000;
748
      else if(mi2rx_strt_rcv)
749
        crc_count <= 3'b000;
750
      else if(send_crc)
751
        crc_count <= crc_count + 1;
752
    end // always @ (posedge phy_rx_clk...
753
 
754
  // These signals are used as intermediate flags to determine
755
  // whether to commit pointer or not to commit pointers
756
  // to the  application
757
  // error_seen helps in tracking errors which could occurs in between
758
  // packet transfer
759
  always @(posedge phy_rx_clk
760
           or negedge reset_n)
761
    begin
762
      if(!reset_n)
763
        begin
764
          commit_write_done <= 1'b1;
765
          error_seen <= 1'b0;
766
        end
767
      else if(mi2rx_strt_rcv)
768
        begin
769
          commit_write_done <= 1'b0;
770
          error_seen <= 1'b0;
771
        end
772
      else
773
        begin
774
          if(commit_write)
775
            commit_write_done <= 1'b1;
776
          if(error)
777
            error_seen <= 1'b1;
778
        end
779
    end // always @ (posedge phy_rx_clk...
780
 
781
  assign look_at_length_field = cf2rx_strp_pad_en &&
782
                                (rcv_length_reg < MIN_FRM_SIZE) && (|rcv_length_reg);
783
  assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
784
         (rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
785
 
786
 
787
 
788
 
789
  assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
790
 
791
  always @(posedge phy_rx_clk
792
           or negedge reset_n)
793
    begin
794
      if(!reset_n)
795
        rcv_byte_count <= 16'h0000;
796
      else if(mi2rx_strt_rcv)
797
        rcv_byte_count <= 16'h0000;
798
      else if(mi2rx_rcv_vld)
799
        rcv_byte_count <= inc_rcv_byte_count;
800
    end // always @ (posedge phy_rx_clk...
801
 
802
  // This signal is asserted wheneven there is no valid transfer on the
803
  // line. Valid transfer is only between mi2rx_strt_rcv and
804
  // mi2rx_end_rcv. In case
805
  // of rewind write transfer becomes invalid. Such data should not be
806
  // written in to the fifo
807
  reg dt_xfr_invalid;
808
  always @(posedge phy_rx_clk
809
           or negedge reset_n)
810
    begin
811
      if(!reset_n)
812
        dt_xfr_invalid <= 1;
813
      else if(rewind_write || ap2rx_rx_fifo_err)
814
        dt_xfr_invalid <= 1;
815
      else if(mi2rx_strt_rcv)
816
        dt_xfr_invalid <= 0;
817
    end
818
  // This is the mux to gather nibbles to two octets for the length field
819
  // of the register
820
  assign inc_length_counter = length_counter + 16'h1;
821
  always @(posedge phy_rx_clk
822
           or negedge reset_n)
823
    begin
824
      if(!reset_n)
825
        begin
826
          rcv_length_reg <= 16'b0;
827
          length_counter <= 16'b0;
828
        end // if (reset_n)
829
      else if (rx_ch_en)
830
        begin
831
          if(mi2rx_strt_rcv)
832
            begin
833
              length_counter <= 16'b0;
834
              rcv_length_reg <= 16'b0;
835
            end
836
          else if(dec_data_len )
837
            length_counter <= inc_length_counter;
838
          else
839
            begin
840
              if(ld_length_byte_1)
841
                begin
842
                  rcv_length_reg[15:8] <= mi2rx_rx_byte;
843
                end
844
            else if(ld_length_byte_2)
845
              begin
846
                rcv_length_reg[7:0] <= mi2rx_rx_byte;
847
              end
848
            end // else: !if(dec_data_len)
849
        end // else: !if(!reset_n)
850
    end // always @ (posedge phy_rx_clk...
851
 
852
  // This signal helps in making sure that when packets are received the
853
  // channel is enabled else ignore the complete packet until next start
854
  // of packet
855
  reg enable_channel;
856
  always @(posedge phy_rx_clk
857
           or negedge reset_n)
858
    begin
859
      if(!reset_n)
860
        enable_channel <= 0;
861
      else if(gen_eop)
862
        enable_channel <= 0;
863
      else if(mi2rx_strt_rcv && rx_ch_en)
864
        enable_channel <= 1;
865
    end
866
 
867
  // This is the decremented padding length register
868
  // Once it reaches zero CRC should follow
869
  assign dec_pad_length = padding_len_reg - 7'h1;
870
  always @(posedge phy_rx_clk
871
           or negedge reset_n)
872
    begin
873
      if(!reset_n)
874
        begin
875
          padding_needed <= 1'b0;
876
          padding_len_reg <= 6'b0;
877
        end
878
      else if(mi2rx_strt_rcv)
879
        begin
880
          padding_needed <= 1'b0;
881
          padding_len_reg <= 6'b0;
882
        end
883
      else if(look_at_length_field &&
884
              check_padding)
885
        begin
886
          padding_len_reg <= MIN_FRM_SIZE - rcv_length_reg[5:0];
887
          padding_needed <= 1'b1;
888
        end
889
      else if(dec_pad_len)
890
        begin
891
          padding_len_reg <= dec_pad_len;
892
          padding_needed <= padding_needed;
893
        end
894
    end // always @ (posedge phy_rx_clk...
895
 
896
  /*********************************************************
897
   Status Generation for Receive packets
898
   Statuses in this case are checked at end of receive packets
899
   and are registered and provided inthe next state along with
900
   rx_sts_valid bit asserted
901
   *********************************************************/
902
 
903
  reg[14:0] fifo_byte_count;
904
  wire [14:0] inc_fifo_byte_count;
905
  wire [14:0] dec_fifo_byte_count;
906
  assign      inc_fifo_byte_count = fifo_byte_count + 15'h1;
907
  assign      dec_fifo_byte_count = fifo_byte_count - 15'h1;
908
 
909
  always @(posedge phy_rx_clk or negedge reset_n)
910
    begin
911
      if(!reset_n)
912
        fifo_byte_count <= 15'd0;
913
      else if(rewind_write || mi2rx_strt_rcv)
914
        fifo_byte_count <= 15'd0;
915
      else if(rx2ap_rx_fsm_wrt)
916
        fifo_byte_count <= inc_fifo_byte_count;
917
    end
918
 
919
  reg        length_sz_mismatch;
920
 
921
  assign rx_sts_dt[31:16] = (e_rx_sts_vld && ap2rx_rx_fifo_err) ?
922
                            {dec_fifo_byte_count + 16'h1} : {fifo_byte_count + 16'h1};
923
  assign rx_sts_dt[15:13] = 3'd0;
924
  assign rx_sts_dt[12] = length_sz_mismatch;
925
  assign rx_sts_dt[11] = 1'b0;
926
  assign rx_sts_dt[10] = large_pkt_reg;
927
  assign rx_sts_dt[7] = lengthfield_err_reg;
928
  assign rx_sts_dt[6] = crc_stat_reg;
929
  assign rx_sts_dt[5] = rx_runt_pkt_reg;
930
  assign rx_sts_dt[4] = rx_fifo_overrun_reg;
931
  assign rx_sts_dt[2] = frm_length_err_reg;
932
  assign rx_sts_dt[1:0] = 2'd0;
933
 
934
  wire        rx_sts_large_pkt;
935
  wire [15:0] rx_sts_bytes_rcvd;
936
  wire        rx_sts_lengthfield_err;
937
  wire        rx_sts_crc_err;
938
  wire        rx_sts_runt_pkt_rcvd;
939
  wire        rx_sts_rx_overrun;
940
  wire        rx_sts_frm_length_err;
941
  wire        rx_sts_len_mismatch;
942
 
943
  assign      rx_sts_bytes_rcvd = rx_sts[31:16];
944
  assign      rx_sts_len_mismatch = rx_sts[12];
945
  assign      rx_sts_large_pkt = rx_sts[10];
946
  assign      rx_sts_lengthfield_err = rx_sts[7];
947
  assign      rx_sts_crc_err = rx_sts[6];
948
  assign      rx_sts_runt_pkt_rcvd = rx_sts[5];
949
  assign      rx_sts_rx_overrun = rx_sts[4];
950
  assign      rx_sts_frm_length_err = rx_sts[2];
951
 
952
 
953
  always @(posedge phy_rx_clk
954
           or negedge reset_n)
955
    begin
956
      if(!reset_n)
957
        begin
958
          crc_stat_reg <= 1'b0;
959
          frm_length_err_reg <= 1'b0;
960
          lengthfield_err_reg <= 1'b0;
961
          rx_fifo_overrun_reg <= 1'b0;
962
          rx_runt_pkt_reg <= 1'b0;
963
          large_pkt_reg <= 1'b0;
964
          length_sz_mismatch <= 1'b0;
965
        end
966
      else if(mi2rx_strt_rcv)
967
        begin
968
          crc_stat_reg <= 1'b0;
969
          frm_length_err_reg <= 1'b0;
970
          lengthfield_err_reg <= 1'b0;
971
          rx_fifo_overrun_reg <= 1'b0;
972
          rx_runt_pkt_reg <= 1'b0;
973
          large_pkt_reg <= 1'b0;
974
          length_sz_mismatch <= 1'b0;
975
        end
976
      else
977
        begin
978
          if(rx_overrun_error)
979
            rx_fifo_overrun_reg <= 1'b1;
980
 
981
          if(lengthfield_error)
982
            lengthfield_err_reg <= 1'b1;
983
 
984
          if(mi2rx_end_rcv && mi2rx_frame_err)
985
            frm_length_err_reg <= 1'b1;
986
 
987
          if(mi2rx_end_rcv)
988
            begin
989
              if(!rc2rx_crc_ok)
990
                crc_stat_reg <= 1'b1;
991
              if(rcv_byte_count[14:0] < 15'd64)
992
                rx_runt_pkt_reg <= 1'b1;
993
              if(rcv_byte_count[14:0] > adj_cf2rx_max_pkt_sz)
994
                large_pkt_reg <= 1'b1;
995
              if( (adj_rcv_byte_count[15:0] != adj_rcv_length_reg) && (adj_rcv_length_reg <= 16'd1500) )
996
                length_sz_mismatch <= 1'b1;
997
            end // if (mi2rx_end_rcv)
998
        end // else: !if(mi2rx_strt_rcv)
999
    end // always @ (posedge phy_rx_clk...
1000
 
1001
  /***************************************************/
1002
  //
1003
  // Additions for Byte operation 
1004
  //
1005
  /***************************************************/
1006
  always @(posedge phy_rx_clk or
1007
           negedge reset_n)
1008
    begin
1009
      if(!reset_n)
1010
        shift_counter <= 3'd0;
1011
      else if(mi2rx_strt_rcv)
1012
        shift_counter <= 3'd0;
1013
      else if(inc_shift_counter)
1014
        shift_counter <= shift_counter + 1;
1015
    end // always @ (posedge phy_rx_clk or...
1016
 
1017
  always @(posedge phy_rx_clk or
1018
           negedge reset_n)
1019
    begin
1020
      if(!reset_n)
1021
        bytes_to_fifo <= 3'd0;
1022
      else if(mi2rx_strt_rcv)
1023
        bytes_to_fifo <= 3'd1;
1024
      else if(send_data_to_fifo)
1025
        bytes_to_fifo <= bytes_to_fifo + 1;
1026
    end // always @ (posedge phy_rx_clk or...
1027
 
1028
  wire[8:0] e_rx_fsm_dt;
1029
  wire      e_rx_fsm_wrt;
1030
  assign    e_rx_fsm_dt[7:0] = buf_latch4;
1031
//  assign    e_rx_fsm_dt[8] = (rx_fifo_full) ? 1'b1 :gen_eop;
1032
  assign    e_rx_fsm_dt[8] = gen_eop;
1033
 
1034
  always @(posedge phy_rx_clk or
1035
           negedge reset_n)
1036
    begin
1037
      if(!reset_n)
1038
        begin
1039
          rx2ap_rx_fsm_dt <= 9'd0;
1040
          rx2ap_rx_fsm_wrt <= 1'b0;
1041
          rx2ap_commit_write <= 1'b0;
1042
          rx2ap_rewind_write <= 1'b0;
1043
        end
1044
      else
1045
        begin
1046
          rx2ap_rx_fsm_wrt <= e_rx_fsm_wrt && (!ap2rx_rx_fifo_err);
1047
          rx2ap_rx_fsm_dt <= e_rx_fsm_dt;
1048
          rx2ap_commit_write <= commit_write;
1049
          rx2ap_rewind_write <= rewind_write;
1050
        end
1051
    end // always @ (posedge phy_rx_clk or...
1052
 
1053
  assign e_rx_fsm_wrt = ((enable_channel &&
1054
                          mi2rx_rcv_vld && !first_dword) ||
1055
                         (enable_channel &&
1056
                          (gen_eop || send_crc)) ||
1057
                         (enable_channel && send_data_to_fifo)) && !rcv_pad_data
1058
                        && !dt_xfr_invalid && !rewind_write;
1059
  assign ld_buf = enable_channel && !rcv_pad_data && (|rcv_byte_count == 1) &&
1060
         (mi2rx_rcv_vld) || send_crc || inc_shift_counter || send_data_to_fifo;
1061
 
1062
  assign ld_buf4 = ld_buf ;
1063
  assign ld_buf3 = ld_buf ;
1064
  assign ld_buf2 = ld_buf ;
1065
  assign ld_buf1 = ld_buf ;
1066
  always @(posedge phy_rx_clk
1067
           or negedge reset_n)
1068
    begin
1069
      if(!reset_n)
1070
        begin
1071
          buf_latch4 <= 8'b0;
1072
          buf_latch3 <= 8'b0;
1073
          buf_latch2 <= 8'b0;
1074
          buf_latch1 <= 8'b0;
1075
          buf_latch0 <= 8'b0;
1076
        end
1077
      else
1078
        begin
1079
          if(ld_buf4)
1080
            buf_latch4 <= buf_latch3;
1081
 
1082
          if(ld_buf3)
1083
            buf_latch3 <= buf_latch2;
1084
 
1085
          if(ld_buf2)
1086
            buf_latch2 <= buf_latch1;
1087
 
1088
          if(ld_buf1)
1089
            buf_latch1 <= buf_latch0;
1090
 
1091
          if (rx_ch_en)
1092
            begin
1093
              if(mi2rx_strt_rcv)
1094
                begin
1095
                  buf_latch0 <= 8'b0;
1096
                end
1097
              else
1098
                begin
1099
                  if(mi2rx_rcv_vld && !rcv_pad_data)
1100
                    begin
1101
                      buf_latch0 <= mi2rx_rx_byte;
1102
                    end
1103
                end // else: !if(mi2rx_strt_rcv)
1104
            end // if (rx_ch_en)
1105
        end // else: !if(!reset_n)
1106
    end // always @ (posedge phy_rx_clk...
1107
 
1108
endmodule

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