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[/] [turbo8051/] [trunk/] [rtl/] [gmac/] [mac/] [g_rx_top.v] - Blame information for rev 76

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1 12 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Tubo 8051 cores MAC Interface Module                        ////
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////                                                              ////
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////  This file is part of the Turbo 8051 cores project           ////
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////  http://www.opencores.org/cores/turbo8051/                   ////
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////                                                              ////
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////  Description                                                 ////
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////  Turbo 8051 definitions.                                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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////  Revision : Mar 2, 2011                                      //// 
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////                                                              ////
19 12 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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 module g_rx_top(
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                app_reset_n,
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                phy_rx_clk,
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                rx_reset_n,
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                app_clk,
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                          scan_mode,
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                rx_sts_vld,
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                rx_sts_bytes_rcvd,
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                rx_sts_large_pkt,
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                rx_sts_lengthfield_err,
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                rx_sts_len_mismatch,
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                rx_sts_crc_err,
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                rx_sts_runt_pkt_rcvd,
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                rx_sts_rx_overrun,
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                rx_sts_frm_length_err,
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                clr_rx_error_from_rx_fsm,
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                rx_fifo_full,
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                rx_dt_wrt,
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                rx_dt_out,
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                rx_commit_wr,
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                commit_write_done,
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                rx_rewind_wr,
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                mi2rx_strt_rcv,
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                mi2rx_rcv_vld,
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                mi2rx_rx_byte,
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                mi2rx_end_rcv,
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                mi2rx_extend,
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                mi2rx_frame_err,
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                mi2rx_end_frame,
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                phy_rx_dv,
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                cf2rx_max_pkt_sz,
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                cf2rx_rx_ch_en,
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                cf2rx_strp_pad_en,
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                cf2rx_snd_crc,
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                cf2df_dfl_single_rx,
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                cf2rx_rcv_runt_pkt_en,
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                cf_macmode,
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                mi2rx_crs,
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                df2rx_dfl_dn,
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                ap2rx_rx_fifo_err,
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      //A200 change Port added for crs based flow control
87 37 dinesha
      phy_crs
88 12 dinesha
               );
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    input               app_reset_n;
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    input               phy_rx_clk;
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    input               rx_reset_n;
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    input               app_clk;
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   input        scan_mode;
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    output              rx_sts_vld;
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    output [15:0]       rx_sts_bytes_rcvd;
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    output              rx_sts_large_pkt;
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    output              rx_sts_lengthfield_err;
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    output              rx_sts_len_mismatch;
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    output              rx_sts_crc_err;
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    output              rx_sts_runt_pkt_rcvd;
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    output              rx_sts_rx_overrun;
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    output              rx_sts_frm_length_err;
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    output              clr_rx_error_from_rx_fsm;
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    input               rx_fifo_full;
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    output              rx_dt_wrt;
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    output [8:0] rx_dt_out;
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    output              rx_commit_wr;
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    output              commit_write_done;
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    output              rx_rewind_wr;
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    input               mi2rx_strt_rcv;
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    input               mi2rx_rcv_vld;
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    input [7:0]          mi2rx_rx_byte;
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    input               mi2rx_end_rcv;
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    input               mi2rx_extend;
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    input               mi2rx_frame_err;
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    input               mi2rx_end_frame;
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    input               phy_rx_dv;
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    input [15:0]        cf2rx_max_pkt_sz;
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    input               cf2rx_rx_ch_en;
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    input               cf2rx_strp_pad_en;
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    input               cf2rx_snd_crc;
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    input               cf2rx_rcv_runt_pkt_en;
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    input               cf_macmode;
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    input  [7:0]        cf2df_dfl_single_rx;
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    input               ap2rx_rx_fifo_err;
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    input               mi2rx_crs;
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    output              df2rx_dfl_dn;
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    //A200 change Port added for crs based flow control
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    input            phy_crs;
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    g_rx_fsm u_rx_fsm(
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              // Status information to Applications
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              .rx_sts_vld(rx_sts_vld),
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              .rx_sts_bytes_rcvd(rx_sts_bytes_rcvd),
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              .rx_sts_large_pkt(rx_sts_large_pkt),
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              .rx_sts_lengthfield_err(rx_sts_lengthfield_err),
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              .rx_sts_len_mismatch(rx_sts_len_mismatch),
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              .rx_sts_crc_err(rx_sts_crc_err),
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              .rx_sts_runt_pkt_rcvd(rx_sts_runt_pkt_rcvd),
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              .rx_sts_rx_overrun(rx_sts_rx_overrun),
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              .rx_sts_frm_length_err(rx_sts_frm_length_err),
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              // Data Signals to Fifo Management Block
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              .clr_rx_error_from_rx_fsm(clr_rx_error_from_rx_fsm),
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              .rx2ap_rx_fsm_wrt(rx_dt_wrt),
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              .rx2ap_rx_fsm_dt(rx_dt_out),
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              // Fifo Control Signal to Fifo Management Block
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              .rx2ap_commit_write(rx_commit_wr),
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              .rx2ap_rewind_write(rx_rewind_wr),
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              // To address filtering block
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              .commit_write_done(commit_write_done),
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              // Global Signals 
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              .reset_n(rx_reset_n),
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              .phy_rx_clk(phy_rx_clk),
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              // Signals from Mii/Rmii block for Receive data 
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              .mi2rx_strt_rcv(mi2rx_strt_rcv),
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              .mi2rx_rcv_vld(mi2rx_rcv_vld),
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              .mi2rx_rx_byte(mi2rx_rx_byte),
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              .mi2rx_end_rcv(mi2rx_end_rcv),
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              .mi2rx_extend(mi2rx_extend),
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              .mi2rx_end_frame(mi2rx_end_frame),
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              .mi2rx_frame_err(mi2rx_frame_err),
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              // Rx fifo management signal to indicate overrun
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              .rx_fifo_full(rx_fifo_full),
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              .ap2rx_rx_fifo_err(ap2rx_rx_fifo_err),
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              // Signal from CRC check block
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              .rc2rx_crc_ok(rc2rx_crc_ok),
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              // Signals from Address filtering block
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              // Signals from Config Management Block
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              .cf2rx_max_pkt_sz(cf2rx_max_pkt_sz),
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              .cf2rx_rx_ch_en(cf2rx_rx_ch_en),
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              .cf2rx_strp_pad_en(cf2rx_strp_pad_en),
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              .cf2rx_snd_crc(cf2rx_snd_crc),
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              .cf2rx_rcv_runt_pkt_en(cf2rx_rcv_runt_pkt_en),
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              .cf2rx_gigabit_xfr(cf_macmode),
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         //A200 change Port added for crs based flow control
183 37 dinesha
         .phy_crs(phy_crs)
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              );
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  g_rx_crc32 u_rx_crc32 (
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              // CRC Valid signal to rx_fsm
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              .rc2rf_crc_ok(rc2rx_crc_ok),
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              // Global Signals
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              .phy_rx_clk(phy_rx_clk),
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              .reset_n(rx_reset_n),
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              // CRC Data signals
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              .mi2rc_strt_rcv(mi2rx_strt_rcv),
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              .mi2rc_rcv_valid(mi2rx_rcv_vld),
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              .mi2rc_rx_byte(mi2rx_rx_byte)
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              );
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  g_deferral_rx U_deferral_rx (
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//0503 Changed .port names to match g_deferral_rx
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            .rx_dfl_dn(df2rx_dfl_dn),
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            .dfl_single(cf2df_dfl_single_rx),
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            .rx_dv(phy_rx_dv),
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//0504      .phy_rx_er(phy_rx_er),
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            .rx_clk(phy_rx_clk),
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            .reset_n(rx_reset_n));
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  endmodule

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