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[/] [turbo8051/] [trunk/] [verif/] [agents/] [ethernet/] [tb_eth_top.v] - Blame information for rev 15

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1 15 dinesha
 
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/*-----------------------------------------------------------------
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|           Ethernet MAC Traffic Generator Testbench                |
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|                                                                   |
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 ------------------------------------------------------------------*/
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/*-----------------------------------------------------------------\
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|  DESCRIPTION:                                                    |
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|  tb_top.v:  Top of MAC testbench hierarchy                       |
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|                                                                  |
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|  Instantiates the following modules:                             |
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|    tb_mii.v:  MII interface                                      |
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|    tb_rmii.v: Reduced MII interface                              |
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|    tb_smii.v: Serial MII interface (add-on module)               |
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|    tb_gmii.v: Gigabit MII interface (add-on module)              |
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|    tb_serd.v: Gigabit SERDES 10-bit interface (add-on module)    |
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|                                                                  |
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|  Included files:                                                 |
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|    tb_conf.v                                                     |
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|    tb_defs.v                                                     |
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|    tb_objs.v                                                     |
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|    tb_tasks.v                                                    |
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|    tb_pktgn.v                                                    |
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\-----------------------------------------------------------------*/
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`timescale 1ns/100ps
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`include "tb_eth_conf.v"
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`include "tb_eth_defs.v"
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module tb_eth_top(
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          REFCLK_50_MHz,            // 50 MHz Reference clock input
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          REFCLK_125_MHz,           // 125 MHz reference clock
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          transmit_enable,          // transmit enable for testbench
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          // Separate interfaces for each MII port type
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          // Full MII, 4-bit interface
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          // Transmit interface
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          MII_RXD,                  // Receive data (output)
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          MII_RX_CLK,               // Receive clock for MII (output)
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          MII_CRS,                  // carrier sense (output)
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          MII_COL,                  // Collision signal for MII (output)
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          MII_RX_DV,                // Receive data valid for MII (output)
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          // Receive interface
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          MII_TXD,                  // Transmit data (input)
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          MII_TX_EN,                // Tx enable (input)
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          MII_TX_CLK,               // Transmit clock (output)
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          // Reduced MII, 2-bit interface
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          // Transmit interface
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          RMII_RXD,                 // Receive data (output)
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          RMII_CRS_DV,              // carrier sense (output)
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          // Receive interface
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          RMII_TXD,                 // Transmit data (input)
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          RMII_TX_EN,               // Tx enable (input)
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          // Serial MII interface
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          SMII_RXD,                 // Receive data (output)
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          SMII_TXD,                 // Transmit data (input)
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          SMII_SYNC,                // SMII SYNC signal (input)              
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          // GMII, 8-bit/10-bit interface
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          // Transmit interface
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          GMII_RXD,                 // Receive data (output)
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          GMII_RX_CLK,              // Receive clock for MII (output)
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          GMII_CRS,                 // carrier sense (output)
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          GMII_COL,                 // Collision signal for MII (output)
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          GMII_RX_DV,               // Receive data valid for MII (output)
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          // Receive interface
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          GMII_TXD,                 // Transmit data (input)
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          GMII_TX_EN,               // Tx enable (input)
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          GMII_TX_CLK,              // Transmit clock (output)
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          GMII_GTX_CLK,             // Gigabit Transmit clock (input), 125 MHz
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              // MII management interface
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          MDIO,                     // serial I/O data
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          MDC                       // clock
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                  );
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   input   REFCLK_50_MHz, REFCLK_125_MHz;
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   input   transmit_enable;
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   // Full-MII signals
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   output [`MII_WIDTH-1: 0]              MII_RXD;
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   output                                MII_RX_CLK,
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                                                                       MII_CRS,
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                                                                       MII_COL,
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                                                                       MII_RX_DV;
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   input  [`MII_WIDTH-1: 0]              MII_TXD;
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   input                                       MII_TX_EN;
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   output                                      MII_TX_CLK;
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   // RMII signals
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   output [`RMII_WIDTH-1: 0]             RMII_RXD;
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   output                                RMII_CRS_DV;
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   input  [`RMII_WIDTH-1: 0]             RMII_TXD;
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   input                                 RMII_TX_EN;
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   // Serial MII signals
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   output                                SMII_RXD;
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   input                                 SMII_TXD;
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   input                                 SMII_SYNC;
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   //Gigabit-MII signals
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   output [`GMII_WIDTH-1: 0]             GMII_RXD;
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   output                                GMII_RX_CLK,
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                                                                       GMII_CRS,
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                                                                       GMII_COL,
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                                                                       GMII_RX_DV;
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   input  [`GMII_WIDTH-1: 0]             GMII_TXD;
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   input                                 GMII_TX_EN;
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   output                                GMII_TX_CLK;
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   input                                 GMII_GTX_CLK;
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120
 
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   // MII Management
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   inout                                 MDIO;
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   input                                 MDC;
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125
`include "tb_eth_objs.v"
126
 
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   // transmit buffer
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   reg [`MAX_PKT_SIZE*8 -1:0]                   transmit_pkt;
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   integer                               transmit_pkt_size;
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131
   // receive buffer
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   reg [`MAX_PKT_SIZE*8 -1:0]            receive_pkt;
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   integer                               receive_pkt_size;
134
 
135
   reg                                   transmit_data_valid;
136
   wire                                  transmit_done;
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   wire                                  receive_data_valid;
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   reg                                   receive_data_available;
139
 
140
   integer   transmit_packet_count, packets_sent, transmit_timer;
141
   reg       transmit_timer_active, transmit_timer_expired, port_tx_busy;
142
 
143
                                        // flag set during transmission of
144
                                        // a packet sequence
145
   //Current transmit packet parameters
146
   integer    current_pkt_size;
147
   reg [47:0] current_src_mac, current_dstn_mac;
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   reg [15:0] current_VLAN_TCI;
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   reg        user_frame; // currently transmitting
150
                                                   // frame from user buffer
151
   integer    user_frame_current_ifg;
152
                                                   // ifg for user frame
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   wire       SMII_TX_EN;
154
 
155
   reg [1:0]   user_crc_option; // CRC generation option for user frames
156
   reg [31:0]  user_crc_value;  // user-supplied CRC for user-generated frames
157
 
158
   // State variables exported to  MII module
159
   integer               mii_transmit_state,
160
                                       mii_receive_state,
161
                                       mii_collision_counter; // for normal cols
162
   reg         mii_SFD_received;
163
 
164
   reg [31:0] event_file;
165
   /* MII port instantiations */
166
   /* Comment out unnecessary interfaces to save simulation cycles */
167
 
168
   tb_mii full_mii(
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                   .port_type               ({port_duplex_status, port_speed[2:0]}),
170
                   .port_tx_enable          (MII_port_tx_enable),
171
                   .port_rx_enable          (MII_port_rx_enable),
172
 
173
                   .REFCLK                  (REFCLK_50_MHz),
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                   .RXD                     (MII_RXD),
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                   .RX_CLK                  (MII_RX_CLK),
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                   .CRS                     (MII_CRS),
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                   .COL                     (MII_COL),
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                   .RX_DV                   (MII_RX_DV),
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                   .TXD                     (MII_TXD),
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                   .TX_EN                   (MII_TX_EN),
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                   .TX_CLK                  (MII_TX_CLK),
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                   .transmit_data_valid     (transmit_data_valid),
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                   .transmit_complete       (transmit_done),
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                   .receive_data_valid      (receive_data_valid),
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                   .event_file              (event_file)
186
 );
187
 
188
 
189
   tb_rmii reduced_mii(
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                   .port_type               ({port_duplex_status, port_speed[2:0]}),
191
                   .port_tx_enable          (RMII_port_tx_enable),
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                   .port_rx_enable          (RMII_port_rx_enable),
193
 
194
                   .REFCLK                  (REFCLK_50_MHz),
195
                   .RXD                     (RMII_RXD),
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                   .CRS_DV                  (RMII_CRS_DV),
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                   .TXD                     (RMII_TXD),
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                   .TX_EN                   (RMII_TX_EN),
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                   .transmit_data_valid     (transmit_data_valid),
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                   .transmit_complete       (transmit_done),
201
                   .receive_data_valid      (receive_data_valid),
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                   .event_file              (event_file)
203
                   );
204
 
205
 
206
   integer i;
207
 
208
   initial
209
    begin
210
       transmit_data_valid = 0;
211
       transmit_packet_count = 0;
212
       receive_data_available =0;
213
       port_mii_type = 3'b111; // set port MII type to invalid
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       packets_sent = 0;
215
       transmit_timer_active = 0;
216
       transmit_timer_expired = 0;
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       port_tx_busy = 0;
218
       user_frame = 0;
219
 
220
       MII_port_tx_enable = 0;
221
       MII_port_rx_enable = 0;
222
       RMII_port_tx_enable = 0;
223
       RMII_port_rx_enable = 0;
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       GMII_port_tx_enable = 0;
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       GMII_port_rx_enable = 0;
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       SMII_port_tx_enable = 0;
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       SMII_port_rx_enable = 0;
228
       SERDES_tx_enable = 0;
229
       SERDES_rx_enable = 0;
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       custom_tx_enable = 0;
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       custom_rx_enable = 0;
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233
       seqno_enable = 0; // do not insert sequence numbers in transmitted pkts
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       timestamp_enable = 0; // do not insert timestamps
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       packet_seq_no = 0;  // initialize sequence number
236
       L3_sequence_number = 0; // initialize IP sequence number
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       flow_type = 0; // default = Layer-2 unicast
238
 
239
       user_crc_option = 0; // enable CRC insertion for user frames, good CRC
240
       user_crc_value = 0;  // defaulr for user_generated CRC
241
 
242
       // set default backoff parameters
243
       collision_limit = 16;
244
       backoff_slots[1] = 32'd2;
245
       backoff_type[1] = 1; // random backoff
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       for (i=2; i <= `MAX_COLLISIONS; i=i+1)
247
        begin
248
           backoff_slots[i] = backoff_slots[i-1] *2;
249
           if (backoff_slots[i] > 1024)
250
            backoff_slots[i] = 1024;  // clamp at 1024 slots
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           backoff_type[i] = 1; // random backoff
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        end // for (i=2; i <= `MAX_COLLISIONS; i=i+1)
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254
       set_default_header_parameters; // initialize headers to default patterns
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       //outfile = $fopen(`PARAM_LOG_FILENAME); // open parameter log
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//        while (1)
257
//        begin 
258
//      #20;
259
//      event_file = "eth_events_log"; // open event log
260
//      #20;
261
//      end
262
    end // initial begin
263
 
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265
 
266
`include "tb_eth_tasks.v"
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268
   //Generate a 1MHz clock for generating transmit timeout
269
   reg clock_1_MHz;
270
   integer clk_cnt_1_MHz;
271
 
272
   initial
273
    begin
274
       clock_1_MHz = 0;
275
       clk_cnt_1_MHz = 0;
276
    end // initial begin
277
 
278
   always @(posedge REFCLK_50_MHz)
279
    begin
280
       if (clk_cnt_1_MHz == 24)
281
        begin
282
           clock_1_MHz = ~clock_1_MHz;
283
           clk_cnt_1_MHz = 0;
284
        end
285
       else
286
        clk_cnt_1_MHz = clk_cnt_1_MHz +1;
287
    end
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289
   //Transmit timeout
290
   always @(posedge clock_1_MHz)
291
    if (transmit_timer_active)
292
     begin
293
        transmit_timer = transmit_timer -1;
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        if (transmit_timer == 0)
295
         begin
296
            $display("%t ns: Testbench transmit timer timed out", $time);
297
            if (`TERMINATE_ON_TRANSMIT_TIMEOUT)
298
             $finish;
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            transmit_timer_expired= 1;
300
            transmit_timer_active = 0;
301
         end // if (transmit_timer == 0)
302
     end // if (transmit_timer_active)
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304
   // Main transmit loop
305
   always @(posedge REFCLK_50_MHz)
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    if ((port_tx_busy == 1) &&
307
        ((port_speed == 0) || (port_speed == 1)))
308
     //only for 10 and 100 Mb ports
309
     begin: main_transmit_block
310
        integer delay, i;
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312
        if (!user_frame)
313
         construct_frame;
314
        transmit_data_valid= 1; // send signal to MII to transmit
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       @(posedge REFCLK_50_MHz)
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        transmit_data_valid = 0;
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        wait(transmit_done);
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319
        packets_sent = packets_sent +1;
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        packet_seq_no = packet_seq_no +1; // increment sequence number;
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322
        // update fields for next packet
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        if (!user_frame)
324
         update_header_parameters;
325
        if ((packets_sent >= transmit_packet_count) ||
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           (transmit_timer_expired)) // transmit no more packets
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         port_tx_busy = 0;
328
        else
329
         begin
330
            // wait for inter-packet spacing
331
            delay = current_ifg - port_min_ifg; // delay in bit times
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            case(port_speed)
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             0: begin // 10 Mb/s = 100 ns per bit
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                for (i = delay*5; i >= 0; i = i-1)
335
                 if (!transmit_timer_expired)
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                  @(posedge REFCLK_50_MHz);
337
             end // case: 0
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339
             1: begin // 100 Mb/s = 10 ns per bit
340
                for (i = delay/2; i >= 0; i = i-1)
341
                 if (!transmit_timer_expired)
342
                 @(posedge REFCLK_50_MHz);
343
             end // case: 1
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345
             default: begin // we shouldn't get here
346
             end // case: default
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348
            endcase // case(port_speed)
349
            if (transmit_timer_expired)
350
             port_tx_busy = 0;
351
         end // else: !if((packets_sent >= transmit_packet_count) ||...
352
     end // block: main_transmit_block
353
 
354
   // Main loop for gigabit port
355
   always @(posedge REFCLK_125_MHz)
356
    if ((port_tx_busy == 1) &&
357
        (port_speed == 2))
358
     begin: main_transmit_block_gigabit
359
        integer delay, i;
360
 
361
        if (!user_frame)
362
         construct_frame;
363
        transmit_data_valid= 1; // send signal to MII to transmit
364
       @(posedge REFCLK_125_MHz)
365
        transmit_data_valid = 0;
366
        wait(transmit_done);
367
 
368
        packets_sent = packets_sent +1;
369
        packet_seq_no = packet_seq_no +1; // increment sequence number;
370
 
371
        // update fields for next packet
372
        if (!user_frame)
373
         update_header_parameters;
374
        if ((packets_sent >= transmit_packet_count) ||
375
            (transmit_timer_expired)) // transmit no more packets
376
         port_tx_busy = 0;
377
        else
378
         begin
379
            // wait for inter-packet spacing
380
            delay = current_ifg - port_min_ifg; // delay in bit times
381
            for (i = delay/8; i >= 0; i = i-1)
382
             if (!transmit_timer_expired)
383
              @(posedge REFCLK_125_MHz);
384
 
385
            if (transmit_timer_expired)
386
             port_tx_busy = 0;
387
         end // else: !if((packets_sent >= transmit_packet_count) ||...
388
     end // block: main_transmit_block_gigabit
389
 
390
`include "tb_eth_pktgn.v" // packet generation tasks
391
 
392
endmodule // testbench
393
 
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