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[/] [turbo8051/] [trunk/] [verif/] [agents/] [ethernet/] [tb_eth_top.v] - Blame information for rev 57

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/*-----------------------------------------------------------------
|           Ethernet MAC Traffic Generator Testbench                |
|                                                                   |
 ------------------------------------------------------------------*/
 
/*-----------------------------------------------------------------\
|  DESCRIPTION:                                                    |
|  tb_top.v:  Top of MAC testbench hierarchy                       |
|                                                                  |
|  Instantiates the following modules:                             |
|    tb_mii.v:  MII interface                                      |
|    tb_rmii.v: Reduced MII interface                              |
|    tb_smii.v: Serial MII interface (add-on module)               |
|    tb_gmii.v: Gigabit MII interface (add-on module)              |
|    tb_serd.v: Gigabit SERDES 10-bit interface (add-on module)    |
|                                                                  |
|  Included files:                                                 |
|    tb_conf.v                                                     |
|    tb_defs.v                                                     |
|    tb_objs.v                                                     |
|    tb_tasks.v                                                    |
|    tb_pktgn.v                                                    |
\-----------------------------------------------------------------*/
 
 
`timescale 1ns/100ps
 
`include "tb_eth_conf.v"
`include "tb_eth_defs.v"
 
module tb_eth_top(
 
          REFCLK_50_MHz,            // 50 MHz Reference clock input
          REFCLK_125_MHz,           // 125 MHz reference clock
          transmit_enable,          // transmit enable for testbench
 
          // Separate interfaces for each MII port type
 
          // Full MII, 4-bit interface
          // Transmit interface
          MII_RXD,                  // Receive data (output)
          MII_RX_CLK,               // Receive clock for MII (output)
          MII_CRS,                  // carrier sense (output)
          MII_COL,                  // Collision signal for MII (output)
          MII_RX_DV,                // Receive data valid for MII (output)
          // Receive interface
          MII_TXD,                  // Transmit data (input)
          MII_TX_EN,                // Tx enable (input)
          MII_TX_CLK,               // Transmit clock (output)
 
          // Reduced MII, 2-bit interface
          // Transmit interface
          RMII_RXD,                 // Receive data (output)
          RMII_CRS_DV,              // carrier sense (output)
          // Receive interface
          RMII_TXD,                 // Transmit data (input)
          RMII_TX_EN,               // Tx enable (input)
 
          // Serial MII interface
          SMII_RXD,                 // Receive data (output)
          SMII_TXD,                 // Transmit data (input)
          SMII_SYNC,                // SMII SYNC signal (input)              
 
          // GMII, 8-bit/10-bit interface
          // Transmit interface
          GMII_RXD,                 // Receive data (output)
          GMII_RX_CLK,              // Receive clock for MII (output)
          GMII_CRS,                 // carrier sense (output)
          GMII_COL,                 // Collision signal for MII (output)
          GMII_RX_DV,               // Receive data valid for MII (output)
          // Receive interface
          GMII_TXD,                 // Transmit data (input)
          GMII_TX_EN,               // Tx enable (input)
          GMII_TX_CLK,              // Transmit clock (output)
          GMII_GTX_CLK,             // Gigabit Transmit clock (input), 125 MHz
 
              // MII management interface
          MDIO,                     // serial I/O data
          MDC                       // clock
                  );
 
 
   input   REFCLK_50_MHz, REFCLK_125_MHz;
 
   input   transmit_enable;
 
   // Full-MII signals
   output [`MII_WIDTH-1: 0]              MII_RXD;
   output                                MII_RX_CLK,
                                                                       MII_CRS,
                                                                       MII_COL,
                                                                       MII_RX_DV;
   input  [`MII_WIDTH-1: 0]              MII_TXD;
   input                                       MII_TX_EN;
   output                                      MII_TX_CLK;
 
   // RMII signals
   output [`RMII_WIDTH-1: 0]             RMII_RXD;
   output                                RMII_CRS_DV;
   input  [`RMII_WIDTH-1: 0]             RMII_TXD;
   input                                 RMII_TX_EN;
 
   // Serial MII signals
   output                                SMII_RXD;
   input                                 SMII_TXD;
   input                                 SMII_SYNC;
 
   //Gigabit-MII signals
   output [`GMII_WIDTH-1: 0]             GMII_RXD;
   output                                GMII_RX_CLK,
                                                                       GMII_CRS,
                                                                       GMII_COL,
                                                                       GMII_RX_DV;
   input  [`GMII_WIDTH-1: 0]             GMII_TXD;
   input                                 GMII_TX_EN;
   output                                GMII_TX_CLK;
   input                                 GMII_GTX_CLK;
 
 
   // MII Management
   inout                                 MDIO;
   input                                 MDC;
 
`include "tb_eth_objs.v"
 
   // transmit buffer
   reg [`MAX_PKT_SIZE*8 -1:0]                   transmit_pkt;
   integer                               transmit_pkt_size;
 
   // receive buffer
   reg [`MAX_PKT_SIZE*8 -1:0]            receive_pkt;
   integer                               receive_pkt_size;
 
   reg                                   transmit_data_valid;
   wire                                  transmit_done;
   wire                                  receive_data_valid;
   reg                                   receive_data_available;
 
   integer   transmit_packet_count, packets_sent, transmit_timer;
   reg       transmit_timer_active, transmit_timer_expired, port_tx_busy;
 
                                        // flag set during transmission of
                                        // a packet sequence
   //Current transmit packet parameters
   integer    current_pkt_size;
   reg [47:0] current_src_mac, current_dstn_mac;
   reg [15:0] current_VLAN_TCI;
   reg        user_frame; // currently transmitting
                                                   // frame from user buffer
   integer    user_frame_current_ifg;
                                                   // ifg for user frame
   wire       SMII_TX_EN;
 
   reg [1:0]   user_crc_option; // CRC generation option for user frames
   reg [31:0]  user_crc_value;  // user-supplied CRC for user-generated frames
 
   // State variables exported to  MII module
   integer               mii_transmit_state,
                                       mii_receive_state,
                                       mii_collision_counter; // for normal cols
   reg         mii_SFD_received;
 
//   wire [31:0] event_file;
   /* MII port instantiations */
   /* Comment out unnecessary interfaces to save simulation cycles */
 
   tb_mii full_mii(
                   .port_type               ({port_duplex_status, port_speed[2:0]}),
                   .port_tx_enable          (MII_port_tx_enable),
                   .port_rx_enable          (MII_port_rx_enable),
 
                   .REFCLK                  (REFCLK_50_MHz),
                   .RXD                     (MII_RXD),
                   .RX_CLK                  (MII_RX_CLK),
                   .CRS                     (MII_CRS),
                   .COL                     (MII_COL),
                   .RX_DV                   (MII_RX_DV),
                   .TXD                     (MII_TXD),
                   .TX_EN                   (MII_TX_EN),
                   .TX_CLK                  (MII_TX_CLK),
                   .transmit_data_valid     (transmit_data_valid),
                   .transmit_complete       (transmit_done),
                   .receive_data_valid      (receive_data_valid),
                   .event_file              (event_file)
 );
 
 
   tb_rmii reduced_mii(
                   .port_type               ({port_duplex_status, port_speed[2:0]}),
                   .port_tx_enable          (RMII_port_tx_enable),
                   .port_rx_enable          (RMII_port_rx_enable),
 
                   .REFCLK                  (REFCLK_50_MHz),
                   .RXD                     (RMII_RXD),
                   .CRS_DV                  (RMII_CRS_DV),
                   .TXD                     (RMII_TXD),
                   .TX_EN                   (RMII_TX_EN),
                   .transmit_data_valid     (transmit_data_valid),
                   .transmit_complete       (transmit_done),
                   .receive_data_valid      (receive_data_valid),
                   .event_file              (event_file)
                   );
 
 
   integer i;
 
   initial
    begin
       transmit_data_valid = 0;
       transmit_packet_count = 0;
       receive_data_available =0;
       port_mii_type = 3'b111; // set port MII type to invalid
       packets_sent = 0;
       transmit_timer_active = 0;
       transmit_timer_expired = 0;
       port_tx_busy = 0;
       user_frame = 0;
 
       MII_port_tx_enable = 0;
       MII_port_rx_enable = 0;
       RMII_port_tx_enable = 0;
       RMII_port_rx_enable = 0;
       GMII_port_tx_enable = 0;
       GMII_port_rx_enable = 0;
       SMII_port_tx_enable = 0;
       SMII_port_rx_enable = 0;
       SERDES_tx_enable = 0;
       SERDES_rx_enable = 0;
       custom_tx_enable = 0;
       custom_rx_enable = 0;
 
       seqno_enable = 0; // do not insert sequence numbers in transmitted pkts
       timestamp_enable = 0; // do not insert timestamps
       packet_seq_no = 0;  // initialize sequence number
       L3_sequence_number = 0; // initialize IP sequence number
       flow_type = 0; // default = Layer-2 unicast
 
       user_crc_option = 0; // enable CRC insertion for user frames, good CRC
       user_crc_value = 0;  // defaulr for user_generated CRC
 
       // set default backoff parameters
       collision_limit = 16;
       backoff_slots[1] = 32'd2;
       backoff_type[1] = 1; // random backoff
       for (i=2; i <= `MAX_COLLISIONS; i=i+1)
        begin
           backoff_slots[i] = backoff_slots[i-1] *2;
           if (backoff_slots[i] > 1024)
            backoff_slots[i] = 1024;  // clamp at 1024 slots
           backoff_type[i] = 1; // random backoff
        end // for (i=2; i <= `MAX_COLLISIONS; i=i+1)
 
       set_default_header_parameters; // initialize headers to default patterns
       //outfile = $fopen(`PARAM_LOG_FILENAME); // open parameter log
//        while (1)
//        begin 
//      #20;
//      event_file = "eth_events_log"; // open event log
//      #20;
//      end
    end // initial begin
 
 
 
`include "tb_eth_tasks.v"
 
   //Generate a 1MHz clock for generating transmit timeout
   reg clock_1_MHz;
   integer clk_cnt_1_MHz;
 
   initial
    begin
       clock_1_MHz = 0;
       clk_cnt_1_MHz = 0;
    end // initial begin
 
   always @(posedge REFCLK_50_MHz)
    begin
       if (clk_cnt_1_MHz == 24)
        begin
           clock_1_MHz = ~clock_1_MHz;
           clk_cnt_1_MHz = 0;
        end
       else
        clk_cnt_1_MHz = clk_cnt_1_MHz +1;
    end
 
   //Transmit timeout
   always @(posedge clock_1_MHz)
    if (transmit_timer_active)
     begin
        transmit_timer = transmit_timer -1;
        if (transmit_timer == 0)
         begin
            $display("%t ns: Testbench transmit timer timed out", $time);
            if (`TERMINATE_ON_TRANSMIT_TIMEOUT)
             $finish;
            transmit_timer_expired= 1;
            transmit_timer_active = 0;
         end // if (transmit_timer == 0)
     end // if (transmit_timer_active)
 
   // Main transmit loop
   always @(posedge REFCLK_50_MHz)
    if ((port_tx_busy == 1) &&
        ((port_speed == 0) || (port_speed == 1)))
     //only for 10 and 100 Mb ports
     begin: main_transmit_block
        integer delay, i;
 
        if (!user_frame)
         construct_frame;
        transmit_data_valid= 1; // send signal to MII to transmit
       @(posedge REFCLK_50_MHz)
        transmit_data_valid = 0;
        wait(transmit_done);
 
        packets_sent = packets_sent +1;
        packet_seq_no = packet_seq_no +1; // increment sequence number;
 
        // update fields for next packet
        if (!user_frame)
         update_header_parameters;
        if ((packets_sent >= transmit_packet_count) ||
           (transmit_timer_expired)) // transmit no more packets
         port_tx_busy = 0;
        else
         begin
            // wait for inter-packet spacing
            delay = current_ifg - port_min_ifg; // delay in bit times
            case(port_speed)
             0: begin // 10 Mb/s = 100 ns per bit
                for (i = delay*5; i >= 0; i = i-1)
                 if (!transmit_timer_expired)
                  @(posedge REFCLK_50_MHz);
             end // case: 0
 
             1: begin // 100 Mb/s = 10 ns per bit
                for (i = delay/2; i >= 0; i = i-1)
                 if (!transmit_timer_expired)
                 @(posedge REFCLK_50_MHz);
             end // case: 1
 
             default: begin // we shouldn't get here
             end // case: default
 
            endcase // case(port_speed)
            if (transmit_timer_expired)
             port_tx_busy = 0;
         end // else: !if((packets_sent >= transmit_packet_count) ||...
     end // block: main_transmit_block
 
   // Main loop for gigabit port
   always @(posedge REFCLK_125_MHz)
    if ((port_tx_busy == 1) &&
        (port_speed == 2))
     begin: main_transmit_block_gigabit
        integer delay, i;
 
        if (!user_frame)
         construct_frame;
        transmit_data_valid= 1; // send signal to MII to transmit
       @(posedge REFCLK_125_MHz)
        transmit_data_valid = 0;
        wait(transmit_done);
 
        packets_sent = packets_sent +1;
        packet_seq_no = packet_seq_no +1; // increment sequence number;
 
        // update fields for next packet
        if (!user_frame)
         update_header_parameters;
        if ((packets_sent >= transmit_packet_count) ||
            (transmit_timer_expired)) // transmit no more packets
         port_tx_busy = 0;
        else
         begin
            // wait for inter-packet spacing
            delay = current_ifg - port_min_ifg; // delay in bit times
            for (i = delay/8; i >= 0; i = i-1)
             if (!transmit_timer_expired)
              @(posedge REFCLK_125_MHz);
 
            if (transmit_timer_expired)
             port_tx_busy = 0;
         end // else: !if((packets_sent >= transmit_packet_count) ||...
     end // block: main_transmit_block_gigabit
 
`include "tb_eth_pktgn.v" // packet generation tasks
 
endmodule // testbench
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [agents/] [ethernet/] [tb_eth_top.v] - Blame information for rev 57

Line No.	Rev	Author	Line
1	15	dinesha
2			`/*-----------------------------------------------------------------`
3			`\| Ethernet MAC Traffic Generator Testbench \|`
4			`\| \|`
5			`------------------------------------------------------------------*/`
6
7			`/*-----------------------------------------------------------------\`
8			`\| DESCRIPTION: \|`
9			`\| tb_top.v: Top of MAC testbench hierarchy \|`
10			`\| \|`
11			`\| Instantiates the following modules: \|`
12			`\| tb_mii.v: MII interface \|`
13			`\| tb_rmii.v: Reduced MII interface \|`
14			`\| tb_smii.v: Serial MII interface (add-on module) \|`
15			`\| tb_gmii.v: Gigabit MII interface (add-on module) \|`
16			`\| tb_serd.v: Gigabit SERDES 10-bit interface (add-on module) \|`
17			`\| \|`
18			`\| Included files: \|`
19			`\| tb_conf.v \|`
20			`\| tb_defs.v \|`
21			`\| tb_objs.v \|`
22			`\| tb_tasks.v \|`
23			`\| tb_pktgn.v \|`
24			`\-----------------------------------------------------------------*/`
25
26
27			`timescale 1ns/100ps
28
29			`include "tb_eth_conf.v"
30			`include "tb_eth_defs.v"
31
32			`module tb_eth_top(`
33
34			`REFCLK_50_MHz, // 50 MHz Reference clock input`
35			`REFCLK_125_MHz, // 125 MHz reference clock`
36			`transmit_enable, // transmit enable for testbench`
37
38			`// Separate interfaces for each MII port type`
39
40			`// Full MII, 4-bit interface`
41			`// Transmit interface`
42			`MII_RXD, // Receive data (output)`
43			`MII_RX_CLK, // Receive clock for MII (output)`
44			`MII_CRS, // carrier sense (output)`
45			`MII_COL, // Collision signal for MII (output)`
46			`MII_RX_DV, // Receive data valid for MII (output)`
47			`// Receive interface`
48			`MII_TXD, // Transmit data (input)`
49			`MII_TX_EN, // Tx enable (input)`
50			`MII_TX_CLK, // Transmit clock (output)`
51
52			`// Reduced MII, 2-bit interface`
53			`// Transmit interface`
54			`RMII_RXD, // Receive data (output)`
55			`RMII_CRS_DV, // carrier sense (output)`
56			`// Receive interface`
57			`RMII_TXD, // Transmit data (input)`
58			`RMII_TX_EN, // Tx enable (input)`
59
60			`// Serial MII interface`
61			`SMII_RXD, // Receive data (output)`
62			`SMII_TXD, // Transmit data (input)`
63			`SMII_SYNC, // SMII SYNC signal (input)`
64
65			`// GMII, 8-bit/10-bit interface`
66			`// Transmit interface`
67			`GMII_RXD, // Receive data (output)`
68			`GMII_RX_CLK, // Receive clock for MII (output)`
69			`GMII_CRS, // carrier sense (output)`
70			`GMII_COL, // Collision signal for MII (output)`
71			`GMII_RX_DV, // Receive data valid for MII (output)`
72			`// Receive interface`
73			`GMII_TXD, // Transmit data (input)`
74			`GMII_TX_EN, // Tx enable (input)`
75			`GMII_TX_CLK, // Transmit clock (output)`
76			`GMII_GTX_CLK, // Gigabit Transmit clock (input), 125 MHz`
77
78			`// MII management interface`
79			`MDIO, // serial I/O data`
80			`MDC // clock`
81			`);`
82
83
84			`input REFCLK_50_MHz, REFCLK_125_MHz;`
85
86			`input transmit_enable;`
87
88			`// Full-MII signals`
89			output [`MII_WIDTH-1: 0] MII_RXD;
90			`output MII_RX_CLK,`
91			`MII_CRS,`
92			`MII_COL,`
93			`MII_RX_DV;`
94			input [`MII_WIDTH-1: 0] MII_TXD;
95			`input MII_TX_EN;`
96			`output MII_TX_CLK;`
97
98			`// RMII signals`
99			output [`RMII_WIDTH-1: 0] RMII_RXD;
100			`output RMII_CRS_DV;`
101			input [`RMII_WIDTH-1: 0] RMII_TXD;
102			`input RMII_TX_EN;`
103
104			`// Serial MII signals`
105			`output SMII_RXD;`
106			`input SMII_TXD;`
107			`input SMII_SYNC;`
108
109			`//Gigabit-MII signals`
110			output [`GMII_WIDTH-1: 0] GMII_RXD;
111			`output GMII_RX_CLK,`
112			`GMII_CRS,`
113			`GMII_COL,`
114			`GMII_RX_DV;`
115			input [`GMII_WIDTH-1: 0] GMII_TXD;
116			`input GMII_TX_EN;`
117			`output GMII_TX_CLK;`
118			`input GMII_GTX_CLK;`
119
120
121			`// MII Management`
122			`inout MDIO;`
123			`input MDC;`
124
125			`include "tb_eth_objs.v"
126
127			`// transmit buffer`
128			reg [`MAX_PKT_SIZE*8 -1:0] transmit_pkt;
129			`integer transmit_pkt_size;`
130
131			`// receive buffer`
132			reg [`MAX_PKT_SIZE*8 -1:0] receive_pkt;
133			`integer receive_pkt_size;`
134
135			`reg transmit_data_valid;`
136			`wire transmit_done;`
137			`wire receive_data_valid;`
138			`reg receive_data_available;`
139
140			`integer transmit_packet_count, packets_sent, transmit_timer;`
141			`reg transmit_timer_active, transmit_timer_expired, port_tx_busy;`
142
143			`// flag set during transmission of`
144			`// a packet sequence`
145			`//Current transmit packet parameters`
146			`integer current_pkt_size;`
147			`reg [47:0] current_src_mac, current_dstn_mac;`
148			`reg [15:0] current_VLAN_TCI;`
149			`reg user_frame; // currently transmitting`
150			`// frame from user buffer`
151			`integer user_frame_current_ifg;`
152			`// ifg for user frame`
153			`wire SMII_TX_EN;`
154
155			`reg [1:0] user_crc_option; // CRC generation option for user frames`
156			`reg [31:0] user_crc_value; // user-supplied CRC for user-generated frames`
157
158			`// State variables exported to MII module`
159			`integer mii_transmit_state,`
160			`mii_receive_state,`
161			`mii_collision_counter; // for normal cols`
162			`reg mii_SFD_received;`
163
164	57	dinesha	`// wire [31:0] event_file;`
165	15	dinesha	`/* MII port instantiations */`
166			`/* Comment out unnecessary interfaces to save simulation cycles */`
167
168			`tb_mii full_mii(`
169			`.port_type ({port_duplex_status, port_speed[2:0]}),`
170			`.port_tx_enable (MII_port_tx_enable),`
171			`.port_rx_enable (MII_port_rx_enable),`
172
173			`.REFCLK (REFCLK_50_MHz),`
174			`.RXD (MII_RXD),`
175			`.RX_CLK (MII_RX_CLK),`
176			`.CRS (MII_CRS),`
177			`.COL (MII_COL),`
178			`.RX_DV (MII_RX_DV),`
179			`.TXD (MII_TXD),`
180			`.TX_EN (MII_TX_EN),`
181			`.TX_CLK (MII_TX_CLK),`
182			`.transmit_data_valid (transmit_data_valid),`
183			`.transmit_complete (transmit_done),`
184			`.receive_data_valid (receive_data_valid),`
185			`.event_file (event_file)`
186			`);`
187
188
189			`tb_rmii reduced_mii(`
190			`.port_type ({port_duplex_status, port_speed[2:0]}),`
191			`.port_tx_enable (RMII_port_tx_enable),`
192			`.port_rx_enable (RMII_port_rx_enable),`
193
194			`.REFCLK (REFCLK_50_MHz),`
195			`.RXD (RMII_RXD),`
196			`.CRS_DV (RMII_CRS_DV),`
197			`.TXD (RMII_TXD),`
198			`.TX_EN (RMII_TX_EN),`
199			`.transmit_data_valid (transmit_data_valid),`
200			`.transmit_complete (transmit_done),`
201			`.receive_data_valid (receive_data_valid),`
202			`.event_file (event_file)`
203			`);`
204
205
206			`integer i;`
207
208			`initial`
209			`begin`
210			`transmit_data_valid = 0;`
211			`transmit_packet_count = 0;`
212			`receive_data_available =0;`
213			`port_mii_type = 3'b111; // set port MII type to invalid`
214			`packets_sent = 0;`
215			`transmit_timer_active = 0;`
216			`transmit_timer_expired = 0;`
217			`port_tx_busy = 0;`
218			`user_frame = 0;`
219
220			`MII_port_tx_enable = 0;`
221			`MII_port_rx_enable = 0;`
222			`RMII_port_tx_enable = 0;`
223			`RMII_port_rx_enable = 0;`
224			`GMII_port_tx_enable = 0;`
225			`GMII_port_rx_enable = 0;`
226			`SMII_port_tx_enable = 0;`
227			`SMII_port_rx_enable = 0;`
228			`SERDES_tx_enable = 0;`
229			`SERDES_rx_enable = 0;`
230			`custom_tx_enable = 0;`
231			`custom_rx_enable = 0;`
232
233			`seqno_enable = 0; // do not insert sequence numbers in transmitted pkts`
234			`timestamp_enable = 0; // do not insert timestamps`
235			`packet_seq_no = 0; // initialize sequence number`
236			`L3_sequence_number = 0; // initialize IP sequence number`
237			`flow_type = 0; // default = Layer-2 unicast`
238
239			`user_crc_option = 0; // enable CRC insertion for user frames, good CRC`
240			`user_crc_value = 0; // defaulr for user_generated CRC`
241
242			`// set default backoff parameters`
243			`collision_limit = 16;`
244			`backoff_slots[1] = 32'd2;`
245			`backoff_type[1] = 1; // random backoff`
246			for (i=2; i <= `MAX_COLLISIONS; i=i+1)
247			`begin`
248			`backoff_slots[i] = backoff_slots[i-1] *2;`
249			`if (backoff_slots[i] > 1024)`
250			`backoff_slots[i] = 1024; // clamp at 1024 slots`
251			`backoff_type[i] = 1; // random backoff`
252			end // for (i=2; i <= `MAX_COLLISIONS; i=i+1)
253
254			`set_default_header_parameters; // initialize headers to default patterns`
255			//outfile = $fopen(`PARAM_LOG_FILENAME); // open parameter log
256			`// while (1)`
257			`// begin`
258			`// #20;`
259			`// event_file = "eth_events_log"; // open event log`
260			`// #20;`
261			`// end`
262			`end // initial begin`
263
264
265
266			`include "tb_eth_tasks.v"
267
268			`//Generate a 1MHz clock for generating transmit timeout`
269			`reg clock_1_MHz;`
270			`integer clk_cnt_1_MHz;`
271
272			`initial`
273			`begin`
274			`clock_1_MHz = 0;`
275			`clk_cnt_1_MHz = 0;`
276			`end // initial begin`
277
278			`always @(posedge REFCLK_50_MHz)`
279			`begin`
280			`if (clk_cnt_1_MHz == 24)`
281			`begin`
282			`clock_1_MHz = ~clock_1_MHz;`
283			`clk_cnt_1_MHz = 0;`
284			`end`
285			`else`
286			`clk_cnt_1_MHz = clk_cnt_1_MHz +1;`
287			`end`
288
289			`//Transmit timeout`
290			`always @(posedge clock_1_MHz)`
291			`if (transmit_timer_active)`
292			`begin`
293			`transmit_timer = transmit_timer -1;`
294			`if (transmit_timer == 0)`
295			`begin`
296			`$display("%t ns: Testbench transmit timer timed out", $time);`
297			if (`TERMINATE_ON_TRANSMIT_TIMEOUT)
298			`$finish;`
299			`transmit_timer_expired= 1;`
300			`transmit_timer_active = 0;`
301			`end // if (transmit_timer == 0)`
302			`end // if (transmit_timer_active)`
303
304			`// Main transmit loop`
305			`always @(posedge REFCLK_50_MHz)`
306			`if ((port_tx_busy == 1) &&`
307			`((port_speed == 0) \|\| (port_speed == 1)))`
308			`//only for 10 and 100 Mb ports`
309			`begin: main_transmit_block`
310			`integer delay, i;`
311
312			`if (!user_frame)`
313			`construct_frame;`
314			`transmit_data_valid= 1; // send signal to MII to transmit`
315			`@(posedge REFCLK_50_MHz)`
316			`transmit_data_valid = 0;`
317			`wait(transmit_done);`
318
319			`packets_sent = packets_sent +1;`
320			`packet_seq_no = packet_seq_no +1; // increment sequence number;`
321
322			`// update fields for next packet`
323			`if (!user_frame)`
324			`update_header_parameters;`
325			`if ((packets_sent >= transmit_packet_count) \|\|`
326			`(transmit_timer_expired)) // transmit no more packets`
327			`port_tx_busy = 0;`
328			`else`
329			`begin`
330			`// wait for inter-packet spacing`
331			`delay = current_ifg - port_min_ifg; // delay in bit times`
332			`case(port_speed)`
333			`0: begin // 10 Mb/s = 100 ns per bit`
334			`for (i = delay*5; i >= 0; i = i-1)`
335			`if (!transmit_timer_expired)`
336			`@(posedge REFCLK_50_MHz);`
337			`end // case: 0`
338
339			`1: begin // 100 Mb/s = 10 ns per bit`
340			`for (i = delay/2; i >= 0; i = i-1)`
341			`if (!transmit_timer_expired)`
342			`@(posedge REFCLK_50_MHz);`
343			`end // case: 1`
344
345			`default: begin // we shouldn't get here`
346			`end // case: default`
347
348			`endcase // case(port_speed)`
349			`if (transmit_timer_expired)`
350			`port_tx_busy = 0;`
351			`end // else: !if((packets_sent >= transmit_packet_count) \|\|...`
352			`end // block: main_transmit_block`
353
354			`// Main loop for gigabit port`
355			`always @(posedge REFCLK_125_MHz)`
356			`if ((port_tx_busy == 1) &&`
357			`(port_speed == 2))`
358			`begin: main_transmit_block_gigabit`
359			`integer delay, i;`
360
361			`if (!user_frame)`
362			`construct_frame;`
363			`transmit_data_valid= 1; // send signal to MII to transmit`
364			`@(posedge REFCLK_125_MHz)`
365			`transmit_data_valid = 0;`
366			`wait(transmit_done);`
367
368			`packets_sent = packets_sent +1;`
369			`packet_seq_no = packet_seq_no +1; // increment sequence number;`
370
371			`// update fields for next packet`
372			`if (!user_frame)`
373			`update_header_parameters;`
374			`if ((packets_sent >= transmit_packet_count) \|\|`
375			`(transmit_timer_expired)) // transmit no more packets`
376			`port_tx_busy = 0;`
377			`else`
378			`begin`
379			`// wait for inter-packet spacing`
380			`delay = current_ifg - port_min_ifg; // delay in bit times`
381			`for (i = delay/8; i >= 0; i = i-1)`
382			`if (!transmit_timer_expired)`
383			`@(posedge REFCLK_125_MHz);`
384
385			`if (transmit_timer_expired)`
386			`port_tx_busy = 0;`
387			`end // else: !if((packets_sent >= transmit_packet_count) \|\|...`
388			`end // block: main_transmit_block_gigabit`
389
390			`include "tb_eth_pktgn.v" // packet generation tasks
391
392			`endmodule // testbench`
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