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[/] [turbo8051/] [trunk/] [verif/] [agents/] [ethernet/] [tb_eth_top.v] - Blame information for rev 76

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/*-----------------------------------------------------------------
|           Ethernet MAC Traffic Generator Testbench                |
|                                                                   |
 ------------------------------------------------------------------*/
 
/*-----------------------------------------------------------------\
|  DESCRIPTION:                                                    |
|  tb_top.v:  Top of MAC testbench hierarchy                       |
|                                                                  |
|  Instantiates the following modules:                             |
|    tb_mii.v:  MII interface                                      |
|    tb_rmii.v: Reduced MII interface                              |
|    tb_smii.v: Serial MII interface (add-on module)               |
|    tb_gmii.v: Gigabit MII interface (add-on module)              |
|    tb_serd.v: Gigabit SERDES 10-bit interface (add-on module)    |
|                                                                  |
|  Included files:                                                 |
|    tb_conf.v                                                     |
|    tb_defs.v                                                     |
|    tb_objs.v                                                     |
|    tb_tasks.v                                                    |
|    tb_pktgn.v                                                    |
\-----------------------------------------------------------------*/
 
 
 
`include "tb_eth_conf.v"
`include "tb_eth_defs.v"
 
module tb_eth_top(
 
          REFCLK_50_MHz,            // 50 MHz Reference clock input
          REFCLK_125_MHz,           // 125 MHz reference clock
          transmit_enable,          // transmit enable for testbench
 
          // Separate interfaces for each MII port type
 
          // Full MII, 4-bit interface
          // Transmit interface
          MII_RXD,                  // Receive data (output)
          MII_RX_CLK,               // Receive clock for MII (output)
          MII_CRS,                  // carrier sense (output)
          MII_COL,                  // Collision signal for MII (output)
          MII_RX_DV,                // Receive data valid for MII (output)
          // Receive interface
          MII_TXD,                  // Transmit data (input)
          MII_TX_EN,                // Tx enable (input)
          MII_TX_CLK,               // Transmit clock (output)
 
          // Reduced MII, 2-bit interface
          // Transmit interface
          RMII_RXD,                 // Receive data (output)
          RMII_CRS_DV,              // carrier sense (output)
          // Receive interface
          RMII_TXD,                 // Transmit data (input)
          RMII_TX_EN,               // Tx enable (input)
 
          // Serial MII interface
          SMII_RXD,                 // Receive data (output)
          SMII_TXD,                 // Transmit data (input)
          SMII_SYNC,                // SMII SYNC signal (input)              
 
          // GMII, 8-bit/10-bit interface
          // Transmit interface
          GMII_RXD,                 // Receive data (output)
          GMII_RX_CLK,              // Receive clock for MII (output)
          GMII_CRS,                 // carrier sense (output)
          GMII_COL,                 // Collision signal for MII (output)
          GMII_RX_DV,               // Receive data valid for MII (output)
          // Receive interface
          GMII_TXD,                 // Transmit data (input)
          GMII_TX_EN,               // Tx enable (input)
          GMII_TX_CLK,              // Transmit clock (output)
          GMII_GTX_CLK,             // Gigabit Transmit clock (input), 125 MHz
 
              // MII management interface
          MDIO,                     // serial I/O data
          MDC                       // clock
                  );
 
 
   input   REFCLK_50_MHz, REFCLK_125_MHz;
 
   input   transmit_enable;
 
   // Full-MII signals
   output [`MII_WIDTH-1: 0]              MII_RXD;
   output                                MII_RX_CLK,
                                                                       MII_CRS,
                                                                       MII_COL,
                                                                       MII_RX_DV;
   input  [`MII_WIDTH-1: 0]              MII_TXD;
   input                                       MII_TX_EN;
   output                                      MII_TX_CLK;
 
   // RMII signals
   output [`RMII_WIDTH-1: 0]             RMII_RXD;
   output                                RMII_CRS_DV;
   input  [`RMII_WIDTH-1: 0]             RMII_TXD;
   input                                 RMII_TX_EN;
 
   // Serial MII signals
   output                                SMII_RXD;
   input                                 SMII_TXD;
   input                                 SMII_SYNC;
 
   //Gigabit-MII signals
   output [`GMII_WIDTH-1: 0]             GMII_RXD;
   output                                GMII_RX_CLK,
                                                                       GMII_CRS,
                                                                       GMII_COL,
                                                                       GMII_RX_DV;
   input  [`GMII_WIDTH-1: 0]             GMII_TXD;
   input                                 GMII_TX_EN;
   output                                GMII_TX_CLK;
   input                                 GMII_GTX_CLK;
 
 
   // MII Management
   inout                                 MDIO;
   input                                 MDC;
 
`include "tb_eth_objs.v"
 
   // transmit buffer
   reg [`MAX_PKT_SIZE*8 -1:0]                   transmit_pkt;
   integer                               transmit_pkt_size;
 
   // receive buffer
   reg [`MAX_PKT_SIZE*8 -1:0]            receive_pkt;
   integer                               receive_pkt_size;
 
   reg                                   transmit_data_valid;
   wire                                  transmit_done;
   wire                                  receive_data_valid;
   reg                                   receive_data_available;
 
   integer   transmit_packet_count, packets_sent, transmit_timer;
   reg       transmit_timer_active, transmit_timer_expired, port_tx_busy;
 
                                        // flag set during transmission of
                                        // a packet sequence
   //Current transmit packet parameters
   integer    current_pkt_size;
   reg [47:0] current_src_mac, current_dstn_mac;
   reg [15:0] current_VLAN_TCI;
   reg        user_frame; // currently transmitting
                                                   // frame from user buffer
   integer    user_frame_current_ifg;
                                                   // ifg for user frame
   wire       SMII_TX_EN;
 
   reg [1:0]   user_crc_option; // CRC generation option for user frames
   reg [31:0]  user_crc_value;  // user-supplied CRC for user-generated frames
 
   // State variables exported to  MII module
   integer               mii_transmit_state,
                                       mii_receive_state,
                                       mii_collision_counter; // for normal cols
   reg         mii_SFD_received;
 
//   wire [31:0] event_file;
   /* MII port instantiations */
   /* Comment out unnecessary interfaces to save simulation cycles */
 
   tb_mii full_mii(
                   .port_type               ({port_duplex_status, port_speed[2:0]}),
                   .port_tx_enable          (MII_port_tx_enable),
                   .port_rx_enable          (MII_port_rx_enable),
 
                   .REFCLK                  (REFCLK_50_MHz),
                   .RXD                     (MII_RXD),
                   .RX_CLK                  (MII_RX_CLK),
                   .CRS                     (MII_CRS),
                   .COL                     (MII_COL),
                   .RX_DV                   (MII_RX_DV),
                   .TXD                     (MII_TXD),
                   .TX_EN                   (MII_TX_EN),
                   .TX_CLK                  (MII_TX_CLK),
                   .transmit_data_valid     (transmit_data_valid),
                   .transmit_complete       (transmit_done),
                   .receive_data_valid      (receive_data_valid),
                   .event_file              (event_file)
 );
 
 
   tb_rmii reduced_mii(
                   .port_type               ({port_duplex_status, port_speed[2:0]}),
                   .port_tx_enable          (RMII_port_tx_enable),
                   .port_rx_enable          (RMII_port_rx_enable),
 
                   .REFCLK                  (REFCLK_50_MHz),
                   .RXD                     (RMII_RXD),
                   .CRS_DV                  (RMII_CRS_DV),
                   .TXD                     (RMII_TXD),
                   .TX_EN                   (RMII_TX_EN),
                   .transmit_data_valid     (transmit_data_valid),
                   .transmit_complete       (transmit_done),
                   .receive_data_valid      (receive_data_valid),
                   .event_file              (event_file)
                   );
 
 
   integer i;
 
   initial
    begin
       transmit_data_valid = 0;
       transmit_packet_count = 0;
       receive_data_available =0;
       port_mii_type = 3'b111; // set port MII type to invalid
       packets_sent = 0;
       transmit_timer_active = 0;
       transmit_timer_expired = 0;
       port_tx_busy = 0;
       user_frame = 0;
 
       MII_port_tx_enable = 0;
       MII_port_rx_enable = 0;
       RMII_port_tx_enable = 0;
       RMII_port_rx_enable = 0;
       GMII_port_tx_enable = 0;
       GMII_port_rx_enable = 0;
       SMII_port_tx_enable = 0;
       SMII_port_rx_enable = 0;
       SERDES_tx_enable = 0;
       SERDES_rx_enable = 0;
       custom_tx_enable = 0;
       custom_rx_enable = 0;
 
       seqno_enable = 0; // do not insert sequence numbers in transmitted pkts
       timestamp_enable = 0; // do not insert timestamps
       packet_seq_no = 0;  // initialize sequence number
       L3_sequence_number = 0; // initialize IP sequence number
       flow_type = 0; // default = Layer-2 unicast
 
       user_crc_option = 0; // enable CRC insertion for user frames, good CRC
       user_crc_value = 0;  // defaulr for user_generated CRC
 
       // set default backoff parameters
       collision_limit = 16;
       backoff_slots[1] = 32'd2;
       backoff_type[1] = 1; // random backoff
       for (i=2; i <= `MAX_COLLISIONS; i=i+1)
        begin
           backoff_slots[i] = backoff_slots[i-1] *2;
           if (backoff_slots[i] > 1024)
            backoff_slots[i] = 1024;  // clamp at 1024 slots
           backoff_type[i] = 1; // random backoff
        end // for (i=2; i <= `MAX_COLLISIONS; i=i+1)
 
       set_default_header_parameters; // initialize headers to default patterns
       //outfile = $fopen(`PARAM_LOG_FILENAME); // open parameter log
//        while (1)
//        begin 
//      #20;
//      event_file = "eth_events_log"; // open event log
//      #20;
//      end
    end // initial begin
 
 
 
`include "tb_eth_tasks.v"
 
   //Generate a 1MHz clock for generating transmit timeout
   reg clock_1_MHz;
   integer clk_cnt_1_MHz;
 
   initial
    begin
       clock_1_MHz = 0;
       clk_cnt_1_MHz = 0;
    end // initial begin
 
   always @(posedge REFCLK_50_MHz)
    begin
       if (clk_cnt_1_MHz == 24)
        begin
           clock_1_MHz = ~clock_1_MHz;
           clk_cnt_1_MHz = 0;
        end
       else
        clk_cnt_1_MHz = clk_cnt_1_MHz +1;
    end
 
   //Transmit timeout
   always @(posedge clock_1_MHz)
    if (transmit_timer_active)
     begin
        transmit_timer = transmit_timer -1;
        if (transmit_timer == 0)
         begin
            $display("%t ns: Testbench transmit timer timed out", $time);
            if (`TERMINATE_ON_TRANSMIT_TIMEOUT)
             $finish;
            transmit_timer_expired= 1;
            transmit_timer_active = 0;
         end // if (transmit_timer == 0)
     end // if (transmit_timer_active)
 
   // Main transmit loop
   always @(posedge REFCLK_50_MHz)
    if ((port_tx_busy == 1) &&
        ((port_speed == 0) || (port_speed == 1)))
     //only for 10 and 100 Mb ports
     begin: main_transmit_block
        integer delay, i;
 
        if (!user_frame)
         construct_frame;
        transmit_data_valid= 1; // send signal to MII to transmit
       @(posedge REFCLK_50_MHz)
        transmit_data_valid = 0;
        wait(transmit_done);
 
        packets_sent = packets_sent +1;
        packet_seq_no = packet_seq_no +1; // increment sequence number;
 
        // update fields for next packet
        if (!user_frame)
         update_header_parameters;
        if ((packets_sent >= transmit_packet_count) ||
           (transmit_timer_expired)) // transmit no more packets
         port_tx_busy = 0;
        else
         begin
            // wait for inter-packet spacing
            delay = current_ifg - port_min_ifg; // delay in bit times
            case(port_speed)
             0: begin // 10 Mb/s = 100 ns per bit
                for (i = delay*5; i >= 0; i = i-1)
                 if (!transmit_timer_expired)
                  @(posedge REFCLK_50_MHz);
             end // case: 0
 
             1: begin // 100 Mb/s = 10 ns per bit
                for (i = delay/2; i >= 0; i = i-1)
                 if (!transmit_timer_expired)
                 @(posedge REFCLK_50_MHz);
             end // case: 1
 
             default: begin // we shouldn't get here
             end // case: default
 
            endcase // case(port_speed)
            if (transmit_timer_expired)
             port_tx_busy = 0;
         end // else: !if((packets_sent >= transmit_packet_count) ||...
     end // block: main_transmit_block
 
   // Main loop for gigabit port
   always @(posedge REFCLK_125_MHz)
    if ((port_tx_busy == 1) &&
        (port_speed == 2))
     begin: main_transmit_block_gigabit
        integer delay, i;
 
        if (!user_frame)
         construct_frame;
        transmit_data_valid= 1; // send signal to MII to transmit
       @(posedge REFCLK_125_MHz)
        transmit_data_valid = 0;
        wait(transmit_done);
 
        packets_sent = packets_sent +1;
        packet_seq_no = packet_seq_no +1; // increment sequence number;
 
        // update fields for next packet
        if (!user_frame)
         update_header_parameters;
        if ((packets_sent >= transmit_packet_count) ||
            (transmit_timer_expired)) // transmit no more packets
         port_tx_busy = 0;
        else
         begin
            // wait for inter-packet spacing
            delay = current_ifg - port_min_ifg; // delay in bit times
            for (i = delay/8; i >= 0; i = i-1)
             if (!transmit_timer_expired)
              @(posedge REFCLK_125_MHz);
 
            if (transmit_timer_expired)
             port_tx_busy = 0;
         end // else: !if((packets_sent >= transmit_packet_count) ||...
     end // block: main_transmit_block_gigabit
 
`include "tb_eth_pktgn.v" // packet generation tasks
 
endmodule // testbench
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [agents/] [ethernet/] [tb_eth_top.v] - Blame information for rev 76

Line No.	Rev	Author	Line
1	15	dinesha
2			`/*-----------------------------------------------------------------`
3			`\| Ethernet MAC Traffic Generator Testbench \|`
4			`\| \|`
5			`------------------------------------------------------------------*/`
6
7			`/*-----------------------------------------------------------------\`
8			`\| DESCRIPTION: \|`
9			`\| tb_top.v: Top of MAC testbench hierarchy \|`
10			`\| \|`
11			`\| Instantiates the following modules: \|`
12			`\| tb_mii.v: MII interface \|`
13			`\| tb_rmii.v: Reduced MII interface \|`
14			`\| tb_smii.v: Serial MII interface (add-on module) \|`
15			`\| tb_gmii.v: Gigabit MII interface (add-on module) \|`
16			`\| tb_serd.v: Gigabit SERDES 10-bit interface (add-on module) \|`
17			`\| \|`
18			`\| Included files: \|`
19			`\| tb_conf.v \|`
20			`\| tb_defs.v \|`
21			`\| tb_objs.v \|`
22			`\| tb_tasks.v \|`
23			`\| tb_pktgn.v \|`
24			`\-----------------------------------------------------------------*/`
25
26
27
28			`include "tb_eth_conf.v"
29			`include "tb_eth_defs.v"
30
31			`module tb_eth_top(`
32
33			`REFCLK_50_MHz, // 50 MHz Reference clock input`
34			`REFCLK_125_MHz, // 125 MHz reference clock`
35			`transmit_enable, // transmit enable for testbench`
36
37			`// Separate interfaces for each MII port type`
38
39			`// Full MII, 4-bit interface`
40			`// Transmit interface`
41			`MII_RXD, // Receive data (output)`
42			`MII_RX_CLK, // Receive clock for MII (output)`
43			`MII_CRS, // carrier sense (output)`
44			`MII_COL, // Collision signal for MII (output)`
45			`MII_RX_DV, // Receive data valid for MII (output)`
46			`// Receive interface`
47			`MII_TXD, // Transmit data (input)`
48			`MII_TX_EN, // Tx enable (input)`
49			`MII_TX_CLK, // Transmit clock (output)`
50
51			`// Reduced MII, 2-bit interface`
52			`// Transmit interface`
53			`RMII_RXD, // Receive data (output)`
54			`RMII_CRS_DV, // carrier sense (output)`
55			`// Receive interface`
56			`RMII_TXD, // Transmit data (input)`
57			`RMII_TX_EN, // Tx enable (input)`
58
59			`// Serial MII interface`
60			`SMII_RXD, // Receive data (output)`
61			`SMII_TXD, // Transmit data (input)`
62			`SMII_SYNC, // SMII SYNC signal (input)`
63
64			`// GMII, 8-bit/10-bit interface`
65			`// Transmit interface`
66			`GMII_RXD, // Receive data (output)`
67			`GMII_RX_CLK, // Receive clock for MII (output)`
68			`GMII_CRS, // carrier sense (output)`
69			`GMII_COL, // Collision signal for MII (output)`
70			`GMII_RX_DV, // Receive data valid for MII (output)`
71			`// Receive interface`
72			`GMII_TXD, // Transmit data (input)`
73			`GMII_TX_EN, // Tx enable (input)`
74			`GMII_TX_CLK, // Transmit clock (output)`
75			`GMII_GTX_CLK, // Gigabit Transmit clock (input), 125 MHz`
76
77			`// MII management interface`
78			`MDIO, // serial I/O data`
79			`MDC // clock`
80			`);`
81
82
83			`input REFCLK_50_MHz, REFCLK_125_MHz;`
84
85			`input transmit_enable;`
86
87			`// Full-MII signals`
88			output [`MII_WIDTH-1: 0] MII_RXD;
89			`output MII_RX_CLK,`
90			`MII_CRS,`
91			`MII_COL,`
92			`MII_RX_DV;`
93			input [`MII_WIDTH-1: 0] MII_TXD;
94			`input MII_TX_EN;`
95			`output MII_TX_CLK;`
96
97			`// RMII signals`
98			output [`RMII_WIDTH-1: 0] RMII_RXD;
99			`output RMII_CRS_DV;`
100			input [`RMII_WIDTH-1: 0] RMII_TXD;
101			`input RMII_TX_EN;`
102
103			`// Serial MII signals`
104			`output SMII_RXD;`
105			`input SMII_TXD;`
106			`input SMII_SYNC;`
107
108			`//Gigabit-MII signals`
109			output [`GMII_WIDTH-1: 0] GMII_RXD;
110			`output GMII_RX_CLK,`
111			`GMII_CRS,`
112			`GMII_COL,`
113			`GMII_RX_DV;`
114			input [`GMII_WIDTH-1: 0] GMII_TXD;
115			`input GMII_TX_EN;`
116			`output GMII_TX_CLK;`
117			`input GMII_GTX_CLK;`
118
119
120			`// MII Management`
121			`inout MDIO;`
122			`input MDC;`
123
124			`include "tb_eth_objs.v"
125
126			`// transmit buffer`
127			reg [`MAX_PKT_SIZE*8 -1:0] transmit_pkt;
128			`integer transmit_pkt_size;`
129
130			`// receive buffer`
131			reg [`MAX_PKT_SIZE*8 -1:0] receive_pkt;
132			`integer receive_pkt_size;`
133
134			`reg transmit_data_valid;`
135			`wire transmit_done;`
136			`wire receive_data_valid;`
137			`reg receive_data_available;`
138
139			`integer transmit_packet_count, packets_sent, transmit_timer;`
140			`reg transmit_timer_active, transmit_timer_expired, port_tx_busy;`
141
142			`// flag set during transmission of`
143			`// a packet sequence`
144			`//Current transmit packet parameters`
145			`integer current_pkt_size;`
146			`reg [47:0] current_src_mac, current_dstn_mac;`
147			`reg [15:0] current_VLAN_TCI;`
148			`reg user_frame; // currently transmitting`
149			`// frame from user buffer`
150			`integer user_frame_current_ifg;`
151			`// ifg for user frame`
152			`wire SMII_TX_EN;`
153
154			`reg [1:0] user_crc_option; // CRC generation option for user frames`
155			`reg [31:0] user_crc_value; // user-supplied CRC for user-generated frames`
156
157			`// State variables exported to MII module`
158			`integer mii_transmit_state,`
159			`mii_receive_state,`
160			`mii_collision_counter; // for normal cols`
161			`reg mii_SFD_received;`
162
163	57	dinesha	`// wire [31:0] event_file;`
164	15	dinesha	`/* MII port instantiations */`
165			`/* Comment out unnecessary interfaces to save simulation cycles */`
166
167			`tb_mii full_mii(`
168			`.port_type ({port_duplex_status, port_speed[2:0]}),`
169			`.port_tx_enable (MII_port_tx_enable),`
170			`.port_rx_enable (MII_port_rx_enable),`
171
172			`.REFCLK (REFCLK_50_MHz),`
173			`.RXD (MII_RXD),`
174			`.RX_CLK (MII_RX_CLK),`
175			`.CRS (MII_CRS),`
176			`.COL (MII_COL),`
177			`.RX_DV (MII_RX_DV),`
178			`.TXD (MII_TXD),`
179			`.TX_EN (MII_TX_EN),`
180			`.TX_CLK (MII_TX_CLK),`
181			`.transmit_data_valid (transmit_data_valid),`
182			`.transmit_complete (transmit_done),`
183			`.receive_data_valid (receive_data_valid),`
184			`.event_file (event_file)`
185			`);`
186
187
188			`tb_rmii reduced_mii(`
189			`.port_type ({port_duplex_status, port_speed[2:0]}),`
190			`.port_tx_enable (RMII_port_tx_enable),`
191			`.port_rx_enable (RMII_port_rx_enable),`
192
193			`.REFCLK (REFCLK_50_MHz),`
194			`.RXD (RMII_RXD),`
195			`.CRS_DV (RMII_CRS_DV),`
196			`.TXD (RMII_TXD),`
197			`.TX_EN (RMII_TX_EN),`
198			`.transmit_data_valid (transmit_data_valid),`
199			`.transmit_complete (transmit_done),`
200			`.receive_data_valid (receive_data_valid),`
201			`.event_file (event_file)`
202			`);`
203
204
205			`integer i;`
206
207			`initial`
208			`begin`
209			`transmit_data_valid = 0;`
210			`transmit_packet_count = 0;`
211			`receive_data_available =0;`
212			`port_mii_type = 3'b111; // set port MII type to invalid`
213			`packets_sent = 0;`
214			`transmit_timer_active = 0;`
215			`transmit_timer_expired = 0;`
216			`port_tx_busy = 0;`
217			`user_frame = 0;`
218
219			`MII_port_tx_enable = 0;`
220			`MII_port_rx_enable = 0;`
221			`RMII_port_tx_enable = 0;`
222			`RMII_port_rx_enable = 0;`
223			`GMII_port_tx_enable = 0;`
224			`GMII_port_rx_enable = 0;`
225			`SMII_port_tx_enable = 0;`
226			`SMII_port_rx_enable = 0;`
227			`SERDES_tx_enable = 0;`
228			`SERDES_rx_enable = 0;`
229			`custom_tx_enable = 0;`
230			`custom_rx_enable = 0;`
231
232			`seqno_enable = 0; // do not insert sequence numbers in transmitted pkts`
233			`timestamp_enable = 0; // do not insert timestamps`
234			`packet_seq_no = 0; // initialize sequence number`
235			`L3_sequence_number = 0; // initialize IP sequence number`
236			`flow_type = 0; // default = Layer-2 unicast`
237
238			`user_crc_option = 0; // enable CRC insertion for user frames, good CRC`
239			`user_crc_value = 0; // defaulr for user_generated CRC`
240
241			`// set default backoff parameters`
242			`collision_limit = 16;`
243			`backoff_slots[1] = 32'd2;`
244			`backoff_type[1] = 1; // random backoff`
245			for (i=2; i <= `MAX_COLLISIONS; i=i+1)
246			`begin`
247			`backoff_slots[i] = backoff_slots[i-1] *2;`
248			`if (backoff_slots[i] > 1024)`
249			`backoff_slots[i] = 1024; // clamp at 1024 slots`
250			`backoff_type[i] = 1; // random backoff`
251			end // for (i=2; i <= `MAX_COLLISIONS; i=i+1)
252
253			`set_default_header_parameters; // initialize headers to default patterns`
254			//outfile = $fopen(`PARAM_LOG_FILENAME); // open parameter log
255			`// while (1)`
256			`// begin`
257			`// #20;`
258			`// event_file = "eth_events_log"; // open event log`
259			`// #20;`
260			`// end`
261			`end // initial begin`
262
263
264
265			`include "tb_eth_tasks.v"
266
267			`//Generate a 1MHz clock for generating transmit timeout`
268			`reg clock_1_MHz;`
269			`integer clk_cnt_1_MHz;`
270
271			`initial`
272			`begin`
273			`clock_1_MHz = 0;`
274			`clk_cnt_1_MHz = 0;`
275			`end // initial begin`
276
277			`always @(posedge REFCLK_50_MHz)`
278			`begin`
279			`if (clk_cnt_1_MHz == 24)`
280			`begin`
281			`clock_1_MHz = ~clock_1_MHz;`
282			`clk_cnt_1_MHz = 0;`
283			`end`
284			`else`
285			`clk_cnt_1_MHz = clk_cnt_1_MHz +1;`
286			`end`
287
288			`//Transmit timeout`
289			`always @(posedge clock_1_MHz)`
290			`if (transmit_timer_active)`
291			`begin`
292			`transmit_timer = transmit_timer -1;`
293			`if (transmit_timer == 0)`
294			`begin`
295			`$display("%t ns: Testbench transmit timer timed out", $time);`
296			if (`TERMINATE_ON_TRANSMIT_TIMEOUT)
297			`$finish;`
298			`transmit_timer_expired= 1;`
299			`transmit_timer_active = 0;`
300			`end // if (transmit_timer == 0)`
301			`end // if (transmit_timer_active)`
302
303			`// Main transmit loop`
304			`always @(posedge REFCLK_50_MHz)`
305			`if ((port_tx_busy == 1) &&`
306			`((port_speed == 0) \|\| (port_speed == 1)))`
307			`//only for 10 and 100 Mb ports`
308			`begin: main_transmit_block`
309			`integer delay, i;`
310
311			`if (!user_frame)`
312			`construct_frame;`
313			`transmit_data_valid= 1; // send signal to MII to transmit`
314			`@(posedge REFCLK_50_MHz)`
315			`transmit_data_valid = 0;`
316			`wait(transmit_done);`
317
318			`packets_sent = packets_sent +1;`
319			`packet_seq_no = packet_seq_no +1; // increment sequence number;`
320
321			`// update fields for next packet`
322			`if (!user_frame)`
323			`update_header_parameters;`
324			`if ((packets_sent >= transmit_packet_count) \|\|`
325			`(transmit_timer_expired)) // transmit no more packets`
326			`port_tx_busy = 0;`
327			`else`
328			`begin`
329			`// wait for inter-packet spacing`
330			`delay = current_ifg - port_min_ifg; // delay in bit times`
331			`case(port_speed)`
332			`0: begin // 10 Mb/s = 100 ns per bit`
333			`for (i = delay*5; i >= 0; i = i-1)`
334			`if (!transmit_timer_expired)`
335			`@(posedge REFCLK_50_MHz);`
336			`end // case: 0`
337
338			`1: begin // 100 Mb/s = 10 ns per bit`
339			`for (i = delay/2; i >= 0; i = i-1)`
340			`if (!transmit_timer_expired)`
341			`@(posedge REFCLK_50_MHz);`
342			`end // case: 1`
343
344			`default: begin // we shouldn't get here`
345			`end // case: default`
346
347			`endcase // case(port_speed)`
348			`if (transmit_timer_expired)`
349			`port_tx_busy = 0;`
350			`end // else: !if((packets_sent >= transmit_packet_count) \|\|...`
351			`end // block: main_transmit_block`
352
353			`// Main loop for gigabit port`
354			`always @(posedge REFCLK_125_MHz)`
355			`if ((port_tx_busy == 1) &&`
356			`(port_speed == 2))`
357			`begin: main_transmit_block_gigabit`
358			`integer delay, i;`
359
360			`if (!user_frame)`
361			`construct_frame;`
362			`transmit_data_valid= 1; // send signal to MII to transmit`
363			`@(posedge REFCLK_125_MHz)`
364			`transmit_data_valid = 0;`
365			`wait(transmit_done);`
366
367			`packets_sent = packets_sent +1;`
368			`packet_seq_no = packet_seq_no +1; // increment sequence number;`
369
370			`// update fields for next packet`
371			`if (!user_frame)`
372			`update_header_parameters;`
373			`if ((packets_sent >= transmit_packet_count) \|\|`
374			`(transmit_timer_expired)) // transmit no more packets`
375			`port_tx_busy = 0;`
376			`else`
377			`begin`
378			`// wait for inter-packet spacing`
379			`delay = current_ifg - port_min_ifg; // delay in bit times`
380			`for (i = delay/8; i >= 0; i = i-1)`
381			`if (!transmit_timer_expired)`
382			`@(posedge REFCLK_125_MHz);`
383
384			`if (transmit_timer_expired)`
385			`port_tx_busy = 0;`
386			`end // else: !if((packets_sent >= transmit_packet_count) \|\|...`
387			`end // block: main_transmit_block_gigabit`
388
389			`include "tb_eth_pktgn.v" // packet generation tasks
390
391			`endmodule // testbench`
392
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