OpenCores
URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [agents/] [spi/] [st_m25p20a/] [acdc_check.v] - Blame information for rev 76

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 dinesha
// Author: Mehdi SEBBANE
2
// May 2002
3
// Verilog model
4
// project: M25P20 25 MHz,
5
// release: 1.4.1
6
 
7
 
8
 
9
// These Verilog HDL models are provided "as is" without warranty
10
// of any kind, included but not limited to, implied warranty
11
// of merchantability and fitness for a particular purpose.
12
 
13
 
14
 
15
 
16
 
17
`ifdef SFLASH_SPDUP
18
`include "parameter_fast.v"
19
`else
20
`include "parameter.v"
21
`endif
22
 
23
module acdc_check (c, d, s, hold, write_op, read_op);
24
 
25
   input c;
26
   input d;
27
   input s;
28
   input hold;
29
   input write_op;
30
   input read_op;
31
 
32
   ////////////////
33
   // TIMING VALUES
34
   ////////////////
35
   time t_C_rise;
36
   time t_C_fall;
37
   time t_H_rise;
38
   time t_H_fall;
39
   time t_S_rise;
40
   time t_S_fall;
41
   time t_D_change;
42
   time high_time;
43
   time low_time;
44
   ////////////////
45
 
46
   reg toggle;
47
 
48
   initial
49
   begin
50
      high_time = 100000;
51
      low_time = 100000;
52
      toggle = 1'b0;
53
   end
54
 
55
   //--------------------------------------------
56
   // This process checks pulses length on pin /S
57
   //--------------------------------------------
58
   always
59
   begin : shsl_watch
60
      @(posedge s);
61
      begin
62
         if ($time != 0)
63
         begin
64
            t_S_rise = $time;
65
            @(negedge s);
66
            t_S_fall = $time;
67
            if ((t_S_fall - t_S_rise) < `TSHSL)
68
            begin
69
               $display("ERROR : tSHSL condition violated");
70
            end
71
         end
72
      end
73
   end
74
 
75
   //----------------------------------------------------
76
   // This process checks select and deselect setup 
77
   // and hold timings 
78
   //----------------------------------------------------
79
   always
80
   begin : s_watch
81
      @(s);
82
      if ((s == 1'b0) && (hold != 1'b0))
83
      begin
84
         if ($time != 0)
85
         begin
86
            t_S_fall = $time;
87
            if (c == 1'b1)
88
            begin
89
               if ( ($time - t_C_rise) < `TCHSL)
90
               begin
91
                  $display("ERROR :tCHSL condition violated");
92
               end
93
            end
94
            else if (c == 1'b0)
95
            begin
96
               @(c);
97
               if ( ($time - t_S_fall) < `TSLCH)
98
               begin
99
                  $display("ERROR :tSLCH condition violated");
100
               end
101
            end
102
         end
103
      end
104
      if ((s == 1'b1) && (hold != 1'b0))
105
      begin
106
         if ($time != 0)
107
         begin
108
            t_S_rise = $time;
109
            if (c == 1'b1)
110
            begin
111
               if ( ($time - t_C_rise) < `TCHSH)
112
               begin
113
                  $display("ERROR :tCHSH condition violated");
114
               end
115
            end
116
            else if (c == 1'b0)
117
            begin
118
               @(c);
119
               if ( ($time - t_S_rise) < `TSHCH )
120
               begin
121
                  $display("ERROR :tSHCH condition violated");
122
               end
123
            end
124
         end
125
      end
126
   end
127
 
128
   //---------------------------------
129
   // This process checks hold timings
130
   //---------------------------------
131
   always
132
   begin : hold_watch
133
      @(hold);
134
      if ((hold == 1'b0) && (s == 1'b0))
135
      begin
136
         if ($time != 0)
137
         begin
138
            t_H_fall = $time ;
139
            if ( (t_H_fall - t_C_rise) < `TCHHL)
140
            begin
141
               $display("ERROR : tCHHL condition violated");
142
            end
143
 
144
            @(posedge c);
145
            if( ($time - t_H_fall) < `THLCH)
146
            begin
147
               $display("ERROR : tHLCH condition violated");
148
            end
149
         end
150
      end
151
 
152
 
153
      if ((hold == 1'b1) && (s == 1'b0))
154
      begin
155
         if ($time != 0)
156
         begin
157
            t_H_rise = $time ;
158
            if ( (t_H_rise - t_C_rise) < `TCHHH)
159
            begin
160
               $display("ERROR : tCHHH condition violated");
161
            end
162
            @(posedge c);
163
            if( ($time - t_H_fall) < `THHCH)
164
            begin
165
               $display("ERROR : tHHCH condition violated");
166
            end
167
         end
168
      end
169
   end
170
 
171
   //--------------------------------------------------
172
   // This process checks data hold and setup timings
173
   //--------------------------------------------------
174
   always
175
   begin : d_watch
176
      @(d);
177
      if ($time != 0)
178
      begin
179
         t_D_change = $time;
180
         if (c == 1'b1)
181
         begin
182
            if ( ($time - t_C_rise) < `TCHDX)
183
            begin
184
               $display("ERROR : tCHDX condition violated");
185
            end
186
         end
187
         else if (c == 1'b0)
188
         begin
189
            @(c);
190
            if ( ($time - t_D_change) < `TDVCH)
191
            begin
192
               $display("ERROR : tDVCH condition violated");
193
            end
194
         end
195
      end
196
   end
197
 
198
   //-------------------------------------
199
   // This process checks clock high time
200
   //-------------------------------------
201
   always
202
   begin : c_high_watch
203
      @(c);
204
      if ($time != 0)
205
      begin
206
         if (c == 1'b1)
207
         begin
208
            t_C_rise = $time;
209
            @(negedge c);
210
            t_C_fall = $time;
211
            high_time = t_C_fall - t_C_rise;
212
            toggle = ~toggle;
213
            if ((t_C_fall - t_C_rise) < `TCH)
214
            begin
215
               $display("ERROR : tCH condition violated");
216
            end
217
         end
218
      end
219
   end
220
 
221
   //-------------------------------------
222
   // This process checks clock low time
223
   //-------------------------------------
224
   always
225
   begin : c_low_watch
226
      @(c);
227
      if ($time != 0)
228
      begin
229
         if (c == 1'b0)
230
         begin
231
            t_C_fall = $time;
232
            @(posedge c);
233
            t_C_rise = $time;
234
            low_time = t_C_rise - t_C_fall;
235
            toggle = ~toggle;
236
            if ((t_C_rise - t_C_fall) < `TCL)
237
            begin
238
               $display("ERROR : tCL condition violated");
239
            end
240
         end
241
      end
242
   end
243
 
244
   //-----------------------------------------------
245
   // This process checks clock frequency
246
   //-----------------------------------------------
247
//   always @(high_time or low_time or read_op)
248
   always @(toggle or read_op)
249
   begin : freq_watch
250
      if ($time != 0)
251
      begin
252
         if (s == 1'b0)
253
         begin
254
            if (read_op)
255
            begin
256
               if ((high_time + low_time) < `TR)
257
               begin
258
                  $display("ERROR : Clock frequency condition violated for READ instruction: fR>20MHz");
259
               end
260
            end
261
            else if ((high_time + low_time) < `TC)
262
            begin
263
               $display("ERROR : Clock frequency condition violated: fC>25MHz");
264
            end
265
         end
266
      end
267
   end
268
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.