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[/] [turbo8051/] [trunk/] [verif/] [agents/] [spi/] [st_m25p20a/] [memory_access.v] - Blame information for rev 76

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// Author: Mehdi SEBBANE
// May 2002
// Verilog model
// project: M25P20 25 MHz,
// release: 1.4.1
 
 
 
// These Verilog HDL models are provided "as is" without warranty
// of any kind, included but not limited to, implied warranty
// of merchantability and fitness for a particular purpose.
 
 
 
 
 
`ifdef SFLASH_SPDUP
`include "parameter_fast.v"
`else
`include "parameter.v"
`endif
 
module memory_access (add_mem, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, data_to_write, page_add_index, data_to_read);
 
   input[(`NB_BIT_ADD_MEM - 1):0] add_mem;
   input be_enable;
   input se_enable;
   input add_pp_enable;
   input pp_enable;
   input read_enable;
   input data_request;
   input[(`NB_BIT_DATA - 1):0] data_to_write;
   input[(`LSB_TO_CODE_PAGE-1):0] page_add_index;
 
   output[(`NB_BIT_DATA - 1):0] data_to_read;
   reg[(`NB_BIT_DATA - 1):0] data_to_read;
 
   reg[(`NB_BIT_DATA - 1):0] p_prog[0:(`PLENGTH-1)];
   reg[(`NB_BIT_DATA - 1):0] content[0:`TOP_MEM];
   reg[`BIT_TO_CODE_MEM - 1:0] cut_add;
 
   integer i;
   integer deb_zone;
   integer int_add;
   integer int_add_mem;
 
   initial
   begin
      cut_add = 0;
      deb_zone = 0;
      int_add = 0;
      int_add_mem = `BIT_TO_CODE_MEM ;
 
 
      //-------------------------------
      // initialisation of memory array
      //-------------------------------
      $display("NOTE : Load memory with Initial delivery content");
      for(i = 0; i <= `TOP_MEM; i = i + 1)
      begin
         content[i] = 8'b11111111 ;
      end
      $display("NOTE : Initial Load End");
 
      for(i = 0; i <= (`PLENGTH-1); i = i + 1)
      begin
         p_prog[i] = 8'b11111111 ;
      end
 
      //Added to Preload Data
      `ifdef PRELOAD_SPI_FLASH
         if(`SPI_PRELOAD_FNAME !== "") begin
            $display("Load Memory from file: %s",`SPI_PRELOAD_FNAME);
            $readmemh (`SPI_PRELOAD_FNAME, content);
         end // if (`SPI_PRELOAD_FNAME !== "")
         else $display("Warning: File: %s not found",`SPI_PRELOAD_FNAME);
      `endif
   end
 
   //--------------------------------------------------
   //                PROCESS MEMORY
   //--------------------------------------------------
 
   always
   begin
      @(negedge add_pp_enable )
 
         for(i = 0; i <= (`PLENGTH-1); i = i + 1)
         begin
            p_prog[i] = 8'b11111111 ;
         end
   end
 
   always
   begin
      @(page_add_index)
      if ($time != 0)
      begin
         if (page_add_index !== 8'bxxxxxxxx)
         begin
            if (add_pp_enable == 1'b1 && pp_enable == 1'b0)
            begin
               p_prog[page_add_index] <= data_to_write ;
            end
         end
      end
   end
 
   always
      @(posedge se_enable or posedge read_enable or add_pp_enable)
      if ($time != 0)
      begin
         for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
         begin
            cut_add[i] = add_mem[i];
         end
      end
 
   always
      @(posedge data_request)
      if ($time != 0)
      begin
         if (read_enable)
         begin
            int_add = cut_add;
            //---------------------------------------------------------
            // Read instruction
            //---------------------------------------------------------
            if (int_add > `TOP_MEM)
            begin
               for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
               begin
                  cut_add[i] = 1'b0;
               end
               int_add = 0; // roll over at the end of mem array
            end
            data_to_read <= content[int_add] ;
            cut_add <= cut_add + 1; // next address 
         end
      end
 
   always
      @(negedge read_enable)
      if ($time != 0)
      begin
         for(i = 0; i <= `NB_BIT_DATA - 1; i = i + 1)
         begin
            data_to_read[i] <= 1'b0 ;
         end
      end
 
   //--------------------------------------------------------
   // Page program instruction
   // To find the first adress of the memory to be programmed
   //--------------------------------------------------------
   always
      @(add_pp_enable)
         if (add_pp_enable == 1'b1)
         begin
            int_add_mem = cut_add;
            int_add = `TOP_MEM + 1;
            while (int_add > int_add_mem)
            begin
               int_add = int_add - `PLENGTH ;
            end
         end
 
      //----------------------------------------------------
      // Sector erase instruction
      // To find the first adress of the sector to be erased
      //----------------------------------------------------
   wire #1 se_enable_dly = se_enable;
   always
      @(posedge se_enable_dly)
         begin
            int_add = cut_add & `MASK_SECTOR ;
         end
   //----------------------------------------------------
   // Write or erase cycle execution
   //----------------------------------------------------
   always
      @(posedge pp_enable)
      if ($time != 0)            // to avoid any corruption at initialization of variables
      begin
         for(i = 0; i <= (`PLENGTH - 1); i = i + 1)
         begin
            content[int_add + i] = p_prog[i] & content[int_add + i];
         end
      end
 
   always
      @(negedge be_enable)
      if ($time != 0)            // to avoid any corruption at initialization of variables
      begin
         for(i = 0; i <= `TOP_MEM; i = i + 1)
         begin
            content[i] = 8'b11111111;
         end
      end
 
   always
      @(negedge se_enable)
      if ($time != 0)            // to avoid any corruption at initialization of variables
      begin
         for(i = int_add; i <= (int_add + (`SSIZE / `NB_BIT_DATA) - 1); i = i + 1)
         begin
            content[i] = 8'b11111111;
         end
      end
 
endmodule

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[/] [turbo8051/] [trunk/] [verif/] [agents/] [spi/] [st_m25p20a/] [memory_access.v] - Blame information for rev 76

Line No.	Rev	Author	Line
1	15	dinesha	`// Author: Mehdi SEBBANE`
2			`// May 2002`
3			`// Verilog model`
4			`// project: M25P20 25 MHz,`
5			`// release: 1.4.1`
6
7
8
9			`// These Verilog HDL models are provided "as is" without warranty`
10			`// of any kind, included but not limited to, implied warranty`
11			`// of merchantability and fitness for a particular purpose.`
12
13
14
15
16
17			`ifdef SFLASH_SPDUP
18			`include "parameter_fast.v"
19			`else
20			`include "parameter.v"
21			`endif
22
23			`module memory_access (add_mem, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, data_to_write, page_add_index, data_to_read);`
24
25			input[(`NB_BIT_ADD_MEM - 1):0] add_mem;
26			`input be_enable;`
27			`input se_enable;`
28			`input add_pp_enable;`
29			`input pp_enable;`
30			`input read_enable;`
31			`input data_request;`
32			input[(`NB_BIT_DATA - 1):0] data_to_write;
33			input[(`LSB_TO_CODE_PAGE-1):0] page_add_index;
34
35			output[(`NB_BIT_DATA - 1):0] data_to_read;
36			reg[(`NB_BIT_DATA - 1):0] data_to_read;
37
38			reg[(`NB_BIT_DATA - 1):0] p_prog[0:(`PLENGTH-1)];
39			reg[(`NB_BIT_DATA - 1):0] content[0:`TOP_MEM];
40			reg[`BIT_TO_CODE_MEM - 1:0] cut_add;
41
42			`integer i;`
43			`integer deb_zone;`
44			`integer int_add;`
45			`integer int_add_mem;`
46
47			`initial`
48			`begin`
49			`cut_add = 0;`
50			`deb_zone = 0;`
51			`int_add = 0;`
52			int_add_mem = `BIT_TO_CODE_MEM ;
53
54
55			`//-------------------------------`
56			`// initialisation of memory array`
57			`//-------------------------------`
58			`$display("NOTE : Load memory with Initial delivery content");`
59			for(i = 0; i <= `TOP_MEM; i = i + 1)
60			`begin`
61			`content[i] = 8'b11111111 ;`
62			`end`
63			`$display("NOTE : Initial Load End");`
64
65			for(i = 0; i <= (`PLENGTH-1); i = i + 1)
66			`begin`
67			`p_prog[i] = 8'b11111111 ;`
68			`end`
69
70			`//Added to Preload Data`
71			`ifdef PRELOAD_SPI_FLASH
72			if(`SPI_PRELOAD_FNAME !== "") begin
73			$display("Load Memory from file: %s",`SPI_PRELOAD_FNAME);
74			$readmemh (`SPI_PRELOAD_FNAME, content);
75			end // if (`SPI_PRELOAD_FNAME !== "")
76			else $display("Warning: File: %s not found",`SPI_PRELOAD_FNAME);
77			`endif
78			`end`
79
80			`//--------------------------------------------------`
81			`// PROCESS MEMORY`
82			`//--------------------------------------------------`
83
84			`always`
85			`begin`
86			`@(negedge add_pp_enable )`
87
88			for(i = 0; i <= (`PLENGTH-1); i = i + 1)
89			`begin`
90			`p_prog[i] = 8'b11111111 ;`
91			`end`
92			`end`
93
94			`always`
95			`begin`
96			`@(page_add_index)`
97			`if ($time != 0)`
98			`begin`
99			`if (page_add_index !== 8'bxxxxxxxx)`
100			`begin`
101			`if (add_pp_enable == 1'b1 && pp_enable == 1'b0)`
102			`begin`
103			`p_prog[page_add_index] <= data_to_write ;`
104			`end`
105			`end`
106			`end`
107			`end`
108
109			`always`
110			`@(posedge se_enable or posedge read_enable or add_pp_enable)`
111			`if ($time != 0)`
112			`begin`
113			for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
114			`begin`
115			`cut_add[i] = add_mem[i];`
116			`end`
117			`end`
118
119			`always`
120			`@(posedge data_request)`
121			`if ($time != 0)`
122			`begin`
123			`if (read_enable)`
124			`begin`
125			`int_add = cut_add;`
126			`//---------------------------------------------------------`
127			`// Read instruction`
128			`//---------------------------------------------------------`
129			if (int_add > `TOP_MEM)
130			`begin`
131			for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
132			`begin`
133			`cut_add[i] = 1'b0;`
134			`end`
135			`int_add = 0; // roll over at the end of mem array`
136			`end`
137			`data_to_read <= content[int_add] ;`
138			`cut_add <= cut_add + 1; // next address`
139			`end`
140			`end`
141
142			`always`
143			`@(negedge read_enable)`
144			`if ($time != 0)`
145			`begin`
146			for(i = 0; i <= `NB_BIT_DATA - 1; i = i + 1)
147			`begin`
148			`data_to_read[i] <= 1'b0 ;`
149			`end`
150			`end`
151
152			`//--------------------------------------------------------`
153			`// Page program instruction`
154			`// To find the first adress of the memory to be programmed`
155			`//--------------------------------------------------------`
156			`always`
157			`@(add_pp_enable)`
158			`if (add_pp_enable == 1'b1)`
159			`begin`
160			`int_add_mem = cut_add;`
161			int_add = `TOP_MEM + 1;
162			`while (int_add > int_add_mem)`
163			`begin`
164			int_add = int_add - `PLENGTH ;
165			`end`
166			`end`
167
168			`//----------------------------------------------------`
169			`// Sector erase instruction`
170			`// To find the first adress of the sector to be erased`
171			`//----------------------------------------------------`
172			`wire #1 se_enable_dly = se_enable;`
173			`always`
174			`@(posedge se_enable_dly)`
175			`begin`
176			int_add = cut_add & `MASK_SECTOR ;
177			`end`
178			`//----------------------------------------------------`
179			`// Write or erase cycle execution`
180			`//----------------------------------------------------`
181			`always`
182			`@(posedge pp_enable)`
183			`if ($time != 0) // to avoid any corruption at initialization of variables`
184			`begin`
185			for(i = 0; i <= (`PLENGTH - 1); i = i + 1)
186			`begin`
187			`content[int_add + i] = p_prog[i] & content[int_add + i];`
188			`end`
189			`end`
190
191			`always`
192			`@(negedge be_enable)`
193			`if ($time != 0) // to avoid any corruption at initialization of variables`
194			`begin`
195			for(i = 0; i <= `TOP_MEM; i = i + 1)
196			`begin`
197			`content[i] = 8'b11111111;`
198			`end`
199			`end`
200
201			`always`
202			`@(negedge se_enable)`
203			`if ($time != 0) // to avoid any corruption at initialization of variables`
204			`begin`
205			for(i = int_add; i <= (int_add + (`SSIZE / `NB_BIT_DATA) - 1); i = i + 1)
206			`begin`
207			`content[i] = 8'b11111111;`
208			`end`
209			`end`
210
211			`endmodule`