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[/] [turbo8051/] [trunk/] [verif/] [defs/] [tb_defines.v] - Blame information for rev 15

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//
// Functional Description:
//
// This has all defines used in TB
//
// *************************************************************************
 
// For Top level simulations
`define TB_TOP_LEVEL_SIM  1
`define TB_RAND_SEED      0
 
// RTL - Instance 
`define TB_TOP          tb_top
`define CHIP_TOP        `TB_TOP.chip_top
`define CORE            `TB_TOP.u_core
 
// TB - Global
`define TB_GLBL         `TB_TOP.tb_glbl
 
`define TB_AGENTS_GMAC  `TB_TOP.u_tb_eth
`define TB_AGENTS_UART  `TB_TOP.tb_uart
 

Line No.	Rev	Author	Line
1	15	dinesha	`//`
2			`// Functional Description:`
3			`//`
4			`// This has all defines used in TB`
5			`//`
6			`// *************************************************************************`
7
8			`// For Top level simulations`
9			`define TB_TOP_LEVEL_SIM 1
10			`define TB_RAND_SEED 0
11
12			`// RTL - Instance`
13			`define TB_TOP tb_top
14			`define CHIP_TOP `TB_TOP.chip_top
15			`define CORE `TB_TOP.u_core
16
17			`// TB - Global`
18			`define TB_GLBL `TB_TOP.tb_glbl
19
20			`define TB_AGENTS_GMAC `TB_TOP.u_tb_eth
21			`define TB_AGENTS_UART `TB_TOP.tb_uart
22

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[/] [turbo8051/] [trunk/] [verif/] [defs/] [tb_defines.v] - Blame information for rev 15