OpenCores
URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [log/] [gmac_test_2.log] - Blame information for rev 79

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 78 dinesha
Reading pref.tcl
2
 
3
# 2020.3
4
 
5
# vsim -do "run.do" -c tb_top "+gmac_test_2"
6
# Start time: 19:19:11 on Aug 18,2022
7
# //  ModelSim Microsemi 2020.3 Jul 13 2020 Linux 5.15.0-41-generic
8
# //
9
# //  Copyright 1991-2020 Mentor Graphics Corporation
10
# //  All Rights Reserved.
11
# //
12
# //  ModelSim Microsemi and its associated documentation contain trade
13
# //  secrets and commercial or financial information that are the property of
14
# //  Mentor Graphics Corporation and are privileged, confidential,
15
# //  and exempt from disclosure under the Freedom of Information Act,
16
# //  5 U.S.C. Section 552. Furthermore, this information
17
# //  is prohibited from disclosure under the Trade Secrets Act,
18
# //  18 U.S.C. Section 1905.
19
# //
20
# Loading sv_std.std
21
# Loading work.tb_top
22
# Loading work.digital_core
23
# Loading work.clkgen
24
# Loading work.clk_ctl
25
# Loading work.wb_crossbar
26
# Loading work.g_mac_top
27
# Loading work.g_dpath_ctrl
28
# Loading work.g_eth_parser
29
# Loading work.g_mac_core
30
# Loading work.g_rx_top
31
# Loading work.g_rx_fsm
32
# Loading work.half_dup_dble_reg
33
# Loading work.g_rx_crc32
34
# Loading work.g_deferral_rx
35
# Loading work.g_md_intf
36
# Loading work.g_tx_top
37
# Loading work.g_deferral
38
# Loading work.g_tx_fsm
39
# Loading work.g_tx_crc32
40
# Loading work.toggle_sync
41
# Loading work.g_cfg_mgmt
42
# Loading work.s2f_sync
43
# Loading work.generic_register
44
# Loading work.req_register
45
# Loading work.stat_counter
46
# Loading work.generic_intr_stat_reg
47
# Loading work.g_mii_intf
48
# Loading work.async_fifo
49
# Loading work.wb_rd_mem2mem
50
# Loading work.wb_wr_mem2mem
51
# Loading work.uart_core
52
# Loading work.uart_cfg
53
# Loading work.stat_register
54
# Loading work.uart_txfsm
55
# Loading work.uart_rxfsm
56
# Loading work.double_sync_low
57
# Loading work.spi_core
58
# Loading work.spi_if
59
# Loading work.spi_ctl
60
# Loading work.spi_cfg
61
# Loading work.oc8051_top
62
# Loading work.oc8051_decoder
63
# Loading work.oc8051_alu
64
# Loading work.oc8051_multiply
65
# Loading work.oc8051_divide
66
# Loading work.oc8051_ram_top
67
# Loading work.oc8051_ram_256x8_two_bist
68
# Loading work.oc8051_alu_src_sel
69
# Loading work.oc8051_comp
70
# Loading work.oc8051_cy_select
71
# Loading work.oc8051_indi_addr
72
# Loading work.oc8051_memory_interface
73
# Loading work.oc8051_sfr
74
# Loading work.oc8051_acc
75
# Loading work.oc8051_b_register
76
# Loading work.oc8051_sp
77
# Loading work.oc8051_dptr
78
# Loading work.oc8051_psw
79
# Loading work.oc8051_ports
80
# Loading work.oc8051_int
81
# Loading work.oc8051_tc
82
# Loading work.oc8051_tc2
83
# Loading work.oc8051_xrom
84
# Loading work.oc8051_xram
85
# Loading work.tb_eth_top
86
# Loading work.tb_mii
87
# Loading work.tb_rmii
88
# Loading work.uart_agent
89
# Loading work.m25p20
90
# Loading work.memory_access
91
# Loading work.acdc_check
92
# Loading work.internal_logic
93
# Loading work.AT45DB321
94
# Loading work.tb_glbl
95
# Loading work.bit_register
96
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u_core'.  Expected 50, found 44.
97
#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core File: ../tb/tb_top.v Line: 162
98
# ** Warning: (vsim-3015) [PCDPC] - Port size (8) does not match connection size (4) for port 'phy_txd'. The port definition is at: ../../rtl/core/digital_core.v(29).
99
#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core File: ../tb/tb_top.v Line: 162
100
# ** Warning: (vsim-3015) [PCDPC] - Port size (8) does not match connection size (4) for port 'phy_rxd'. The port definition is at: ../../rtl/core/digital_core.v(35).
101
#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core File: ../tb/tb_top.v Line: 162
102
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'scan_mode'.
103
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'scan_enable'.
104
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_clk'.
105
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_in'.
106
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_out'.
107
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_out_en'.
108
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u_rxfifo'.  Expected 14, found 12.
109
#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/uart/uart_core.v Line: 200
110
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(200): [TFMPC] - Missing connection for port 'afull'.
111
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(200): [TFMPC] - Missing connection for port 'aempty'.
112
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u_txfifo'.  Expected 14, found 12.
113
#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/uart/uart_core.v Line: 216
114
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(216): [TFMPC] - Missing connection for port 'afull'.
115
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(216): [TFMPC] - Missing connection for port 'aempty'.
116
# ** Warning: (vsim-PLI-3003) [TOFD] - System task or function '$shm_open' is not defined.
117
#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: ../tb/tb_top.v Line: 397
118
# ** Warning: (vsim-PLI-3003) [TOFD] - System task or function '$shm_probe' is not defined.
119
#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: ../tb/tb_top.v Line: 398
120
# do run.do
121
# i : 02
122
# i : 00
123
# i : 08
124
# i : 12
125
# i : 00
126
# i : 64
127
# i : 80
128
# i : fe
129
# i : 75
130
# i : 81
131
# NOTE : Load memory with Initial delivery content
132
# NOTE : Initial Load End
133
# --> Dumpping the design
134
# ** Error (suppressible): (vsim-12023) Cannot execute undefined system task/function '$shm_open'
135
#    Time: 0 ps  Iteration: 0  Process: /tb_top/#INITIAL#395 File: ../tb/tb_top.v Line: 397
136
# ** Error (suppressible): (vsim-12023) Cannot execute undefined system task/function '$shm_probe'
137
#    Time: 0 ps  Iteration: 0  Process: /tb_top/#INITIAL#395 File: ../tb/tb_top.v Line: 398
138
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "../test_log_files/test1_events.log" for writing.
139
# No such file or directory. (errno = ENOENT)    : ../testcase/gmac_test2.v(20)
140
#    Time: 0 ps  Iteration: 0  Instance: /tb_top
141
# NOTE: COMMUNICATION (RE)STARTED
142
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 00114501
143
# Config-Write: Id: 1 Addr = 0008, Cfg. Data = 00001616
144
# Clock period configured = 40 ns, data width = 4
145
# Config-Write: Id: 1 Addr = 0024, Cfg. Data = 70407000
146
# Status: End of Transmission Loop
147
# 1260 ns: Starting packet transmission to MAC, size = 64
148
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
149
# Contents:
150
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81
151
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa
152
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20
153
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d
154
# ****
155
#                 7020 ns: Completed packet transmission to MAC
156
# 8060 ns: Starting packet transmission to MAC, size = 65
157
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
158
# Contents:
159
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a
160
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71
161
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c
162
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9
163
# bb
164
# ****
165
#                13900 ns: Completed packet transmission to MAC
166
# Status: End of Waiting Event Loop
167
# 14940 ns: Starting packet transmission to MAC, size = 66
168
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
169
# Contents:
170
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d
171
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73
172
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79
173
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99
174
# f0 ca
175
# ****
176
#                20860 ns: Completed packet transmission to MAC
177
# 21900 ns: Starting packet transmission to MAC, size = 67
178
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
179
# Contents:
180
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79
181
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7
182
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66
183
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1
184
# d6 98 d3
185
# ****
186
#                27900 ns: Completed packet transmission to MAC
187
# 28940 ns: Starting packet transmission to MAC, size = 68
188
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
189
# Contents:
190
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78
191
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98
192
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38
193
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2
194
# d8 8a 95 46
195
# ****
196
#                35020 ns: Completed packet transmission to MAC
197
# 36060 ns: Starting packet transmission to MAC, size = 69
198
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
199
# Contents:
200
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd
201
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae
202
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53
203
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1
204
# 1f dd 21 ca 31
205
# ****
206
#                42220 ns: Completed packet transmission to MAC
207
# 43260 ns: Starting packet transmission to MAC, size = 70
208
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
209
# Contents:
210
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58
211
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49
212
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38
213
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9
214
# 86 25 ec 93 f7 b6
215
# ****
216
#                49500 ns: Completed packet transmission to MAC
217
# 50540 ns: Starting packet transmission to MAC, size = 71
218
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
219
# Contents:
220
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d
221
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd
222
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52
223
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6
224
# 25 32 a2 b2 82 de 56
225
# ****
226
#                56860 ns: Completed packet transmission to MAC
227
# 57900 ns: Starting packet transmission to MAC, size = 72
228
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
229
# Contents:
230
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14
231
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73
232
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93
233
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6
234
# bb 00 0f 69 16 8d 9c 08
235
# ****
236
#                64300 ns: Completed packet transmission to MAC
237
# 65340 ns: Starting packet transmission to MAC, size = 73
238
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
239
# Contents:
240
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59
241
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5
242
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8
243
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68
244
# f0 aa 0f f1 7d 1f 08 38 e7
245
# ****
246
#                71820 ns: Completed packet transmission to MAC
247
# Status: End of Waiting Delay Loop
248
#############################
249
#    TB MII Statistic
250
#  TB TO DUT :
251
#      Frm cnt       :          10
252
#      Byte cnt      :         685
253
#  DUT TO TB :
254
#      Frm cnt       :           0
255
#      Byte cnt      :           0
256
#      Pause Frm  cnt:           0
257
#      Alig Err   cnt:           0
258
#      usized Err cnt:           0
259
#      crc Err    cnt:           0
260
#      Length Err cnt:           0
261
#############################
262 79 dinesha
# TB =>               171820 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected          1
263
# TB =>               171820 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected          2
264 78 dinesha
#
265
# -------------------------------------------------
266
# Test Status
267
# warnings: 0, errors: 2
268
#
269
# -------------------------------------------------
270
# Test Status
271
# warnings: 0, errors: 2
272
#
273
# =========
274
# Test Status: TEST FAILED
275
# =========
276
#
277
# ** Note: $finish    : ../lib/tb_glbl.v(70)
278
#    Time: 172821 ps  Iteration: 0  Instance: /tb_top
279
# End time: 19:19:13 on Aug 18,2022, Elapsed time: 0:00:02
280
# Errors: 2, Warnings: 18

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.